RDL Loop and Void Structure for Chip Package Signal Return Loss
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Solution Overview
Problem
Conventional chip packaging schemes face challenges in maintaining high signal quality as the distance between metal layers decreases, leading to significant capacitance loading and signal return loss, particularly in smaller chip packages.
Innovation Solution
The introduction of loop and void structures in the redistribution layer (RDL) to compensate for capacitance by increasing inductance, thereby reducing capacitive loading and improving signal return loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the distance between metal layers is decreased to reduce chip package size, then chip package size is reduced, but signal quality deteriorates due to increased capacitive loading and signal return loss
Solution Approach 1:
The patent converts the harmful effect of closely spaced metal layers (increased capacitance causing signal return loss) into a beneficial effect by introducing loop structures that generate inductance. This inductance compensates for the excessive capacitance, transforming the harmful capacitive coupling into a balanced impedance relationship that maintains signal quality in miniaturized packages
Solution Approach 2:
The patent changes the electrical parameters of the redistribution layer by incorporating loop structures with specific inductance values. These loop structures modify the impedance characteristics of the signal path, adjusting the inductive reactance to compensate for capacitive effects and maintain proper signal integrity in the reduced-size package configuration
2Ease of manufacture
If conventional redistribution layer design is used with decreased metal layer distance, then manufacturing is simplified, but capacitive loading increases causing signal degradation
Solution Approach 1:
The patent merges the redistribution layer function with additional inductance-providing loop structures within the same metal layers. Rather than adding separate components, the signal routing traces themselves are configured to form loops that generate the necessary inductance, combining routing and impedance compensation functions into a single integrated structure
Solution Approach 2:
The patent uses curved loop trajectories for the signal traces instead of straight lines. These curved paths form circular or elliptical loops that enclose area, generating inductance through the magnetic flux contained within the loop areas. The curvature of these paths is specifically designed to provide the required inductive compensation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The loop and void structures in the RDL reduce signal return loss by about −4 dB in the frequency spectrum between 6.0 GHz and 6.5 GHz, enhancing signal quality and transmission characteristics.
Implementation Method 1
The loop and void structures in the RDL reduce capacitive loading by increasing inductance
Implementation Method 2
the loop and void structures reduce capacitive loading on adjacent metal layers
Data Source
AI summary
Disclosed herein is a chip package and method for fabricating the same are provided that includes a redistribution layer (RDL) with a plurality of loop and void structures. The chip package includes an integrated circuit (IC) die, and a package substrate. The RDL is disposed between the IC die and the package substrate. The RDL has RDL circuitry that connects the IC die to the package substrate. The RDL circuitry includes a first coil formed in a first metal layer and a second coil formed in a second metal layer. A first end of the second coil is coupled to a second end of the first coil by a first via. A second end of the second coil is the IC die.