RDL and Micro-Bump Filter Capacitor for IC Area Reduction

The patent utilizes the vertical dimension by employing multiple metal layers (M1, M2, M3, M4) stacked above each other to form filter and capacitor structures. This multi-layer approach allows the circuit elements to be built in three-dimensional space rather than confined to a single plane, effectively increasing the functional volume without proportionally increasing the chip footprint area

The patent implements nested structures where capacitor plates are formed within the same metal layer structure used for interconnects. Specifically, adjacent metal lines in the same layer or adjacent layers are configured to serve dual purposes as both signal interconnects and capacitor electrodes, creating a nested functional arrangement that maximizes space utilization

The patent achieves thicker effective metal paths by stacking multiple metal layers vertically. The current can flow through multiple thin layers in series, creating an equivalent of a thicker conductive path without requiring wider traces in the lateral plane. This maintains or improves performance while preserving chip area

The patent employs composite conductor structures formed by stacking different metal layers (M1-M4) with varying thicknesses and materials. This composite approach allows optimization of electrical properties (reducing resistance and parasitic capacitance) through the vertical stacking of conductive layers rather than requiring single thick layers that would consume more lateral space