RDL Module-in-Package Layout for Shorter Interconnect Paths
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the large size of modules due to the high number of packages and functions required, leading to increased lead length, propagation delay, and transmission loss, which is exacerbated by the trend towards higher performance and miniaturization.
Innovation Solution
The implementation of a module-in-package (MiP) structure using a redistribution layer (RDL) that integrates two semiconductor packages on opposite sides, providing a short and efficient electrical interconnect, and includes features like shielding frames and embedded antennas to mitigate electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor packages are assembled in a module to achieve higher density and extended functionality, then the electrical functionality and integration density are improved, but the module size increases leading to larger lead length
Solution Approach 1:
The patent merges multiple semiconductor packages into a single module-in-package structure by integrating them on opposite sides of an interconnect substrate. This consolidation reduces the overall module footprint and shortens the lead length between packages, thereby improving electrical performance while maintaining high integration density.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of packages to a three-dimensional module-in-package structure. By stacking packages on opposite sides of the interconnect substrate and using vertical interconnections, the design achieves higher density without increasing the horizontal footprint, thus reducing lead length.
2Adaptability or versatility
If the number of packages in a module is increased to achieve higher integration, then the functionality is extended, but the propagation delay increases
Solution Approach 1:
By merging multiple packages into a tightly integrated module-in-package structure with short interconnect paths, the patent minimizes the propagation delay between packages. The compact design ensures that even as functionality is extended through additional packages, the signal transmission time remains low.
3Productivity
If the module size is increased to accommodate more packages, then the integration density is improved, but the transmission loss increases
Solution Approach 1:
The patent achieves high integration density by utilizing three-dimensional packaging with packages stacked on opposite sides of the interconnect substrate. This vertical arrangement maintains compact horizontal dimensions, keeping transmission paths short and minimizing transmission loss while achieving high density.
4Area of stationary object
If the module is miniaturized to reduce size, then the space efficiency is improved, but the thermal management becomes more difficult
Solution Approach 1:
The patent segments the module into separate packages on opposite sides of the interconnect substrate, each with its own thermal management pathways. This segmentation allows for distributed heat dissipation and multiple thermal vias to be implemented, effectively managing thermal loads in a compact form factor.
5Adaptability or versatility
If more packages are integrated into a module to achieve higher density, then the functionality is extended, but the electromagnetic interference increases
Solution Approach 1:
The patent introduces an interconnect substrate as an intermediary between packages on opposite sides. This substrate provides controlled impedance traces, ground planes, and shielding structures that act as mediators to manage electromagnetic fields and reduce interference between adjacent packages while maintaining functional integration.
Data Source
AI summary
A semiconductor device has a first semiconductor package, second semiconductor package, and RDL. The first semiconductor package is disposed over a first surface of the RDL and the second semiconductor package is disposed over a second surface of the RDL opposite the first surface of the RDL. A carrier is initially disposed over the second surface of the RDL and removed after disposing the first semiconductor package over the first surface of the RDL. The first semiconductor package has a substrate, plurality of conductive pillars formed over the substrate, electrical component disposed over the substrate, and encapsulant deposited around the conductive pillars and electrical component. A shielding frame can be disposed around the electrical component. An antenna can be disposed over the first semiconductor package. A portion of the encapsulant is removed to planarize a surface of the encapsulant and expose the conductive pillars.