Redistribution Package Structure With Thin-Film Passives and Warpage Control
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Solution Overview
Problem
Existing package structures face challenges in reducing size and thickness due to limitations from passive components, leading to space constraints, heat dissipation issues, and structural warping from thermal expansion coefficient mismatches.
Innovation Solution
A package structure with a first redistribution structure, a second redistribution structure containing thin film passive components, conductive pillars, and a molding layer that encapsulates a chip and conductive pillars, along with an insulation structure to balance stress and prevent warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional passive components are used on the substrate surface, then the package structure is simple to manufacture, but the package thickness cannot be reduced and the substrate area is occupied by passive components
Solution Approach 1:
The patent transitions passive components from a planar arrangement on the substrate surface to a three-dimensional stacked configuration. Multiple passive components are vertically stacked above each other, utilizing the Z-axis dimension to reduce substrate area occupation and enable thinner package profiles while maintaining manufacturing feasibility through standardized stacking processes.
Solution Approach 2:
The patent implements nesting by placing smaller passive components within the vertical space above larger components. This nested arrangement allows multiple passive components to occupy the same horizontal footprint by stacking them at different heights, thereby reducing the overall substrate area required and enabling thinner package designs.
2Quantity of substance
If chips are installed on both sides of the substrate to increase capacity, then the substrate area utilization improves, but heat dissipation performance deteriorates
Solution Approach 1:
The patent moves chip mounting from a two-sided planar arrangement to a vertical stacking configuration. Chips are stacked above each other using through-silicon vias and interposer technologies, allowing increased chip quantity without increasing substrate area. This vertical arrangement improves heat dissipation by providing direct thermal pathways from upper chips to the substrate and heat sink structures.
Solution Approach 2:
The patent segments the chip stack into multiple functional layers with independent thermal management. Each chip layer has its own thermal interface and heat dissipation pathway, allowing heat to be efficiently conducted away from each individual chip rather than accumulating in a dense two-sided arrangement.
3Volume of moving object
If chips and passive components are mounted on the substrate surface, then the package structure is compact, but warpage occurs due to thermal expansion coefficient mismatch
Solution Approach 1:
The patent employs composite material structures including matched thermal expansion coefficient materials for the substrate and interposer layers. By selecting materials with compatible thermal properties and creating graded composite structures, the patent reduces differential thermal stress during temperature cycling, thereby minimizing warpage while maintaining compact packaging.
Solution Approach 2:
The patent applies local quality by using stress compensation techniques in specific regions. Reinforcement ribs, stress relief structures, and localized material property adjustments are implemented at critical areas to counteract thermal stress concentrations and prevent warpage in the compact stacked structure.
Data Source
AI summary
The present disclosure relates to the technical field of packaging, and provides a package structure and a related manufacturing method thereof. The package structure includes: a first redistribution structure; a second redistribution structure located on a surface of the first redistribution structure, where the second redistribution structure includes a thin film passive component; a first conductive pillar located on a surface of the second redistribution structure; a chip located on a surface of the first conductive pillar; and a molding layer that is located on the surface of the second redistribution structure and that encapsulates the chip and the first conductive pillar. A size and a thickness of the package are reduced, and the number of I/Os of the package is increased; heat dissipation performance of the package is better; and performance consistency is better.