RDL Semiconductor Packaging for Early Interconnect Failure Testing

Solution Overview

Problem

The manufacturing of miniaturized semiconductor devices is complicated and prone to issues such as poor electrical interconnection and delamination, leading to high yield loss due to the inability to test electrical connections until the completion of the manufacturing process.

Innovation Solution

Incorporation of a dummy conductive member during the manufacturing process allows for early identification of electrical failures, enabling testing before the completion of the semiconductor structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If miniaturized semiconductor devices are manufactured with greater functionality and integrated circuitry, then device capability is improved, but manufacturing complexity increases leading to poor electrical interconnection and delamination

Engineering Contradiction:

Improvedevice functionalityVSAvoidmanufacturing complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent performs electrical testing at intermediate stages during the wafer-level packaging process, before the complete assembly is finished. This preliminary testing action allows detection of electrical interconnection issues early, preventing propagation of defects through subsequent manufacturing steps and reducing yield loss.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism by testing electrical connections at intermediate packaging stages and using this information to identify and correct manufacturing defects. The test results provide feedback about the quality of electrical interconnections, enabling real-time process control and adjustment.

Inventive Principle:

Principle #23Feedback

2Adaptability or versatility

If manufacturing operations are increased to achieve greater functionality in miniaturized devices, then device capability is improved, but yield loss increases due to inability to detect failures early

Engineering Contradiction:

Improvedevice functionalityVSAvoidmanufacturing yield

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent performs electrical testing at intermediate stages during the wafer-level packaging process, before the complete assembly is finished. This preliminary testing action allows detection of electrical interconnection issues early, preventing propagation of defects through subsequent manufacturing steps and reducing yield loss.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism by testing electrical connections at intermediate packaging stages and using this information to identify and correct manufacturing defects. The test results provide feedback about the quality of electrical interconnections, enabling real-time process control and adjustment.

Inventive Principle:

Principle #23Feedback

3Device complexity

If electrical testing is delayed until completion of manufacturing, then device complexity is reduced, but material wastage increases due to undetected failures

Engineering Contradiction:

Improvetesting process simplicityVSAvoidmaterial wastage

Core Design Contradiction:

Device complexityVSLoss of substance

Solution Approach 1:

The patent performs electrical testing at intermediate stages during the wafer-level packaging process, before the complete assembly is finished. This preliminary testing action allows detection of electrical interconnection issues early, preventing propagation of defects through subsequent manufacturing steps and reducing yield loss.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism by testing electrical connections at intermediate packaging stages and using this information to identify and correct manufacturing defects. The test results provide feedback about the quality of electrical interconnections, enabling real-time process control and adjustment.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250266417A1Semiconductor structure and manufacturing method thereof

Publication Date: 2025.08.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.