Redistribution Layer Pad Extension for Die Shift Alignment

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Solution Overview

Problem

In chip first packages, die shift during encapsulation layer formation causes electrical terminals to be misaligned, making it difficult to connect the chip to overlying electronic components, leading to reduced yield.

Innovation Solution

The electronic device package includes a redistribution layer (RDL) with conductive pads having extension portions and a dielectric layer, where the conductive via connection region is closer to the center of curvature of the extension portion than the pad portion, allowing for accurate alignment and connection despite die shift.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a conventional chip first package is used, then the manufacturing process is simple, but the die shift causes misalignment between electrical terminals and reduces yield

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidalignment precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The extension portion is designed and formed in advance during RDL fabrication, before the encapsulation process occurs. This preliminary geometric adjustment ensures that even when die shift happens during encapsulation, the conductive via will still align properly with the extended pad area, thus maintaining alignment precision without complicating the overall manufacturing process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of modifying the entire pad structure or using complex alignment systems, the invention applies a localized geometric modification - extending only the specific portion of the conductive pad that will compensate for the expected die shift. This local quality change maintains manufacturing simplicity while improving alignment precision at the critical connection point

Inventive Principle:
Principle #3Local quality

2Productivity

If die shift is allowed to occur during encapsulation, then the encapsulation process is straightforward, but the electrical terminals are misaligned from their predetermined region

Engineering Contradiction:
Improveencapsulation process efficiencyVSAvoidterminal alignment
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The invention accepts that die shift will occur during encapsulation but converts this harmful effect into a benefit by designing the extension portion to anticipate and compensate for the shift. The pad extension is positioned such that when the die shifts in the expected direction, the conductive via aligns with the extended area rather than the original pad center, thus maintaining connection accuracy without slowing down the encapsulation process

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The extension portion is pre-formed during RDL fabrication before encapsulation takes place. This preliminary geometric adjustment ensures that when die shift occurs during the straightforward encapsulation process, the alignment is already compensated for, maintaining terminal alignment precision while preserving encapsulation efficiency

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11699654B2Electronic device package and method of manufacturing the same
Publication Date: 2023.07.11 ADVANCED SEMICON ENG INC
  • US11699654B2 patent drawing
  • US11699654B2 patent drawing
  • US11699654B2 patent drawing

AI summary

An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.