Redistribution Layer Passivation Opening for Precise Chip Packaging
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in optimizing device performance due to limitations in redistribution layer (RDL) formation, which affects the rerouting of connections on chip dies and subsequent packaging processes.
Innovation Solution
A method for forming a redistribution layer (RDL) structure involves depositing a first passivation layer over a chip die, etching via holes, conformally depositing a barrier layer and metal seed layer, filling with conductive material, and covering with a second passivation layer, followed by planarization and etching to expose the RDL feature, enabling efficient rerouting and subsequent packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RDL formation methods are used, then the basic connection routing is achieved, but manufacturing precision and processing consistency deteriorate due to lack of planarization control
Solution Approach 1:
The patent applies planarization treatment before forming the RDL structure to pre-establish a flat surface. This preliminary action ensures that subsequent RDL formation processes occur on a controlled, planar substrate, improving manufacturing precision by eliminating surface irregularities that would cause processing deviations.
Solution Approach 2:
The patent introduces planarization as a process parameter change - transforming the surface topology from non-planar to planar. This parameter change (surface flatness) directly impacts the precision of RDL formation by providing consistent geometric conditions across the entire processing area, reducing variability in RDL dimensions and positioning.
2Productivity
If multiple packaging processes are performed, then connection routing is achieved, but processing time and productivity deteriorate due to repeated handling and alignment steps
Solution Approach 1:
The patent performs planarization treatment in advance, before RDL formation and packaging processes. This preliminary planarization eliminates the need for repeated alignment and adjustment operations during subsequent packaging steps, as the pre-flattened surface ensures consistent positioning and reduces handling time across multiple process stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the formation of RDL structures, improving connection efficiency and reducing processing deviations, leading to better performance and power consumption in semiconductor devices.
Implementation Method 1
a barrier layer and a metal seed layer are conformally deposited over the via holes and the first passivation layer
Implementation Method 2
The via holes may be filled with a conductive material, such as copper, to form an RDL feature
Data Source
AI summary
A method is provided for forming a redistribution layer (RDL) structure. An RDL feature is formed over a die, and the RDL feature is electrically connected to a contact of the die. A passivation layer is formed over the RDL feature. A patterned etch mask layer is formed over the passivation layer, and has an opening over a portion of the RDL feature. The passivation layer is patterned using the patterned etch mask layer disposed thereon. The patterned etch mask layer is removed after the passivation layer is patterned using the patterned etch mask layer disposed thereon. The passivation layer is etched to form a passivation opening in the passivation layer, and the portion of the RDL feature is exposed through the passivation opening.