Protective-Layer RDL Planarization for Fine-Pitch Package Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density and high-frequency packaging due to limitations in the formation of redistribution circuit structures in integrated fan-out packages, which affect the integration density and reliability of electronic components.
Innovation Solution
A method for forming a redistribution layer (RDL) structure using a dual damascene process, involving the creation of trench and via openings in dielectric layers, followed by the deposition of conductive materials and planarization, to achieve high-resolution and fine-pitch RDLs with enhanced electrical reliability and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RDL formation processes are used, then manufacturing simplicity is maintained, but integration density and electrical reliability deteriorate
Solution Approach 1:
The RDL formation process is segmented into multiple sequential steps: forming first dielectric material with first conductive features, then forming second dielectric material with second conductive features. This segmentation allows each layer to be optimized independently for high-density interconnects while maintaining manufacturing feasibility through standardized process modules.
Solution Approach 2:
The patent transitions from planar RDL structures to three-dimensional stacked RDL structures with multiple conductive feature layers at different heights. This dimensional expansion enables significantly higher integration density by utilizing vertical space for additional signal paths and interconnects without increasing the lateral footprint.
2Manufacturing precision
If feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision and electrical reliability worsen
Solution Approach 1:
The patent employs composite dielectric materials with optimized electrical properties, including low-k dielectric materials to reduce signal loss and improve electrical reliability at fine pitch dimensions. The combination of different dielectric materials allows simultaneous achievement of small feature sizes and high electrical performance.
Solution Approach 2:
The patent systematically optimizes critical parameters including dielectric material composition, conductive feature geometry, and layer thicknesses to maintain electrical reliability while reducing feature sizes. Parameter tuning of etch selectivity, deposition conditions, and planarization processes ensures manufacturing precision at sub-micron dimensions.
3Reliability
If multi-layer RDL structure is formed to improve integration density, then electrical reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary planarization of each dielectric layer before forming subsequent conductive features. This preliminary surface preparation ensures uniform deposition and patterning conditions for each layer, simplifying the manufacturing process despite the multi-layer complexity and improving electrical reliability through consistent feature formation.
Solution Approach 2:
The multi-layer RDL structure serves multiple functions simultaneously: providing electrical interconnects, enabling signal routing in three dimensions, offering mechanical support, and allowing independent optimization of different signal paths. This multi-functionality justifies the increased structural complexity by delivering superior electrical reliability and integration density.
Data Source
AI summary
Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.