Redistribution Layer Pre-Testing for Fan-Out Wafer Level Package Yield
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Solution Overview
Problem
Current fan-out wafer level package (FOWLP) technologies are limited by the diameter of large-size wafers, leading to reduced manufacturing capacity and high material waste due to defects in the packaging process, where entire packages with defects must be scrapped, increasing costs and inefficiency.
Innovation Solution
A package structure and manufacturing method that includes a redistribution layer with a first and second distribution region, bonding and testing electrodes, and a mounting layer with conductive pads, allowing for pre-testing of the redistribution layer and electronic devices before packaging, enabling selective exclusion of defective components and reducing waste through a RDL-first process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FOWLP manufacturing process is used where electronic devices are disposed on carrier first and then redistribution layer is formed, then the packaging process can be completed, but defective electronic devices cannot be identified until after packaging, causing entire packages to be scrapped and increasing material waste and costs
Solution Approach 1:
The patent applies preliminary action by forming the redistribution layer on the carrier substrate before disposing electronic devices thereon. This allows the redistribution layer to be pre-manufactured and pre-tested, so that when electronic devices are subsequently bonded to it, only defective devices need to be removed rather than scrapping entire packages. The key innovation is reversing the conventional sequence to enable earlier defect identification and isolation.
Solution Approach 2:
The patent segments the manufacturing process into distinct stages: first forming the redistribution layer independently on the carrier, then separately bonding electronic devices thereto. This segmentation allows the redistribution layer to be tested and validated as a separate component, enabling selective removal of only defective electronic devices while preserving good ones, thereby reducing material waste.
2Productivity
If large-size wafers with diameter of 300 mm are used for manufacturing, then electronic devices can be packaged on wafer at the same time, but the manufacturing capacity is limited due to the fixed wafer size
Solution Approach 1:
The patent transitions from two-dimensional wafer-based manufacturing to three-dimensional panel-based manufacturing. By forming the redistribution layer on a large-area panel substrate rather than a circular wafer, the system可以利用 the full rectangular area of the substrate, significantly increasing the number of electronic devices that can be manufactured simultaneously. The panel level package structure enables utilization of substrates with dimensions exceeding traditional wafer sizes.
3Productivity
If conventional packaging process is used without pre-testing, then the manufacturing process can be completed quickly, but defective components are identified only after packaging, requiring scrapping of entire packages and increasing costs
Solution Approach 1:
The patent implements preliminary testing of the redistribution layer before electronic devices are bonded to it. This pre-testing capability allows defects to be identified and isolated at an early stage, enabling selective removal of only defective components rather than scrapping entire packaged units. The preliminary action of testing before final assembly maintains manufacturing efficiency while dramatically reducing waste and costs.
Data Source
AI summary
A package structure includes a redistribution layer having a first surface, a second surface disposed opposite to the first surface, and at least one sidewall connected to the first surface and the second surface, at least one bonding electrode disposed on the first surface of the redistribution layer, and a mounting layer disposed on the second surface of the redistribution layer. The mounting layer includes a plurality of conductive pads that are spaced apart from each other. At least one of the conductive pads is exposed by the sidewall of the redistribution layer.