Semiconductor Package RDL Recesses Prevent Solder Bridging

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Solution Overview

Problem

Current semiconductor packaging methods face challenges in achieving efficient and cost-effective integration of multiple semiconductor devices within a single package, particularly in preventing solder bridging between contact pads during reflow processes.

Innovation Solution

The method involves forming recesses around the perimeter of contact pads in a second redistribution layer (RDL) within the packaged semiconductor device, using wafer level packaging techniques to create a package-on-package (PoP) or system-in-a-package (SiP) configuration, which prevents solder bridging and enhances manufacturing yields without requiring additional lithography masks or processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wafer level packaging is used to integrate multiple semiconductor devices, then packaging efficiency and integration density are improved, but solder bridging between contact pads occurs during reflow processes

Engineering Contradiction:
Improvepackaging efficiencyVSAvoidsolder bridging prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The contact pad structure is segmented by forming recesses around the perimeter of each contact pad in the second RDL. This segmentation creates isolated regions that prevent solder from bridging between adjacent contact pads during reflow, while maintaining the overall integration density of the wafer level packaging approach.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The recesses formed in the second RDL act as intermediary structures between adjacent contact pads. These recesses create physical barriers that mediate the solder flow during reflow, preventing direct contact between solder on neighboring pads while still allowing the compact PoP or SiP configuration to be achieved.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If traditional packaging methods are used, then solder bridging is avoided, but integration density and packaging efficiency decrease

Engineering Contradiction:
Improvesolder bridging preventionVSAvoidpackaging efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Instead of relying solely on lateral spacing between contact pads (2D approach), the invention introduces a vertical dimension by forming recesses into the second RDL. This dimensional change creates depth-based isolation that prevents solder bridging while maintaining the close proximity needed for high integration density in PoP and SiP configurations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If additional lithography masks or processes are used to prevent solder bridging, then reliability is improved, but manufacturing complexity and costs increase

Engineering Contradiction:
Improvesolder bridging preventionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The formation of recesses around contact pads is merged with the existing second RDL fabrication process. The same lithography and etching steps used to create the second RDL pattern are utilized to define the recesses, eliminating the need for additional masks or separate processing sequences. This integration maintains reliability improvement while avoiding increased manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The second RDL layer serves multiple functions: it provides electrical redistribution and simultaneously creates the recess structures that prevent solder bridging. This multi-functionality eliminates the need for dedicated anti-bridging structures or additional process steps, reducing manufacturing complexity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9418969B2Packaged semiconductor devices and packaging methods
Publication Date: 2016.08.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9418969B2 patent drawing
  • US9418969B2 patent drawing
  • US9418969B2 patent drawing

AI summary

Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.