Redistribution Layer Routing for Multi-Die Packages
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Solution Overview
Problem
In multi-die packages, particularly with wide input/output (I/O) memory devices, it is challenging to find sufficient surface area for routing signal lines due to the small pitch of I/O pins, making it difficult to efficiently connect dies and increase the number of I/O pads.
Innovation Solution
The implementation of a semiconductor device with a polymer layer and conductive pillars, where signal traces are routed in a redistribution layer (RDL) over the pillars, allowing for increased spacing and number of signal traces by positioning them on different interconnect levels than ground and power bridging lines, thereby optimizing surface area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If signal traces are routed on the same level as ground and power bridging lines, then routing is simpler, but available surface area for routing is insufficient due to small pitch of I/O pins
Solution Approach 1:
The patent applies dimensionality change by routing signal traces on different interconnect levels than ground and power bridging lines. This vertical separation in the Z-dimension creates additional routing space without increasing lateral footprint, thereby increasing available surface area for routing while maintaining compact packaging.
2Quantity of substance
If I/O pins are placed with small pitch to increase density, then more I/O pads can be packed, but sufficient surface area for routing signal lines becomes difficult to find
Solution Approach 1:
By utilizing multiple interconnect levels vertically, the patent enables routing of signal lines associated with high-density I/O pins without requiring additional lateral surface area. This allows packing more I/O pads while maintaining sufficient routing space through the third dimension.
Solution Approach 2:
The patent segments the routing function by separating signal traces, ground bridging lines, and power bridging lines onto different interconnect levels. This segmentation allows each type of conductor to be optimized independently and prevents routing conflicts that would arise from mixing all routing on a single level.
3Quantity of substance
If signal traces are positioned closer together to increase density, then more signal lines can be routed, but resistance and line capacitance increase
Solution Approach 1:
The patent routes signal traces on different interconnect levels than ground and power bridging lines, which increases the vertical separation between signal traces. This reduced lateral crowding decreases parasitic capacitance between adjacent lines while maintaining high signal line density through the additional vertical routing capacity.
Data Source
AI summary
Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.