Redistribution Layer Routing Design for Semiconductor Package Stress Mitigation
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging techniques due to high bending stresses at the semiconductor-encapsulant boundary caused by coefficient of thermal expansion (CTE) mismatch, leading to RDL cracking and manufacturing defects in Package-on-Package (PoP) technology.
Innovation Solution
A redistribution layer (RDL) routing design is implemented with wider conductive lines over the encapsulant and integrated circuit dies near the boundary to mitigate stress, featuring varying widths and angles to accommodate CTE mismatch, thereby reducing cracking and manufacturing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RDL routing with uniform width is used, then manufacturing process is simple, but bending stresses at the semiconductor-encapsulant boundary cause RDL cracking and manufacturing defects
Solution Approach 1:
The RDL routing design implements varying line widths at different locations: wider conductive lines are used specifically at the semiconductor-encapsulant boundary region to withstand bending stresses, while narrower lines are used in other regions. This local variation in geometric properties addresses the stress concentration problem at the boundary without unnecessarily increasing complexity throughout the entire RDL structure.
Solution Approach 2:
The invention changes the geometric parameters of the conductive lines by varying their widths based on location. The conductive lines have different widths depending on their position relative to the semiconductor-encapsulant boundary, with wider lines at high-stress regions and narrower lines elsewhere. This parameter variation optimizes both reliability and manufacturing complexity.
2Reliability
If wider conductive lines are used at the boundary to mitigate stress, then RDL cracking resistance improves, but manufacturing precision requirements increase
Solution Approach 1:
The RDL routing design implements varying line widths at different locations: wider conductive lines are used specifically at the semiconductor-encapsulant boundary region to withstand bending stresses, while narrower lines are used in other regions. This local variation in geometric properties addresses the stress concentration problem at the boundary without unnecessarily increasing complexity throughout the entire RDL structure.
Solution Approach 2:
Instead of making all conductive lines uniformly wide throughout the RDL structure, the invention applies the wider line width only partially - specifically at the boundary region where stress concentration occurs. This partial application of the design feature provides the necessary stress mitigation exactly where needed, rather than excessively increasing dimensions across the entire structure, thereby optimizing manufacturing precision requirements.
3Reliability
If RDL routing accommodates CTE mismatch with varying widths and angles, then thermal stress management improves, but device complexity increases
Solution Approach 1:
The RDL routing design implements varying line widths at different locations: wider conductive lines are used specifically at the semiconductor-encapsulant boundary region to withstand bending stresses, while narrower lines are used in other regions. This local variation in geometric properties addresses the stress concentration problem at the boundary without unnecessarily increasing complexity throughout the entire RDL structure.
Solution Approach 2:
The invention changes the geometric parameters of the conductive lines by varying their widths based on location. The conductive lines have different widths depending on their position relative to the semiconductor-encapsulant boundary, with wider lines at high-stress regions and narrower lines elsewhere. This parameter variation optimizes both reliability and manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RDL routing design enhances reliability robustness and reduces manufacturing defects by managing thermal stress at the semiconductor-encapsulant boundary, ensuring more reliable and robust semiconductor package structures.
Implementation Method 1
high bending stresses at the semiconductor-encapsulant boundary caused by coefficient of thermal expansion (CTE) mismatch
Data Source
AI summary
An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, a conductive line electrically connecting a first conductive via to a second conductive via, the conductive line including a first segment over the first integrated circuit die and having a first width, and a second segment over the first integrated circuit die having a second width larger than the first width, the second segment extending over a first boundary between the first integrated circuit die and the encapsulant.