Redistribution Layer Signal Integrity via Vertical Segmentation
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Solution Overview
Problem
In semiconductor packaging, the increased die-to-die signal points lead to significant loss of routing space in the redistribution layer (RDL), limiting the number of signal traces that can be arranged and resulting in adverse signal integrity due to crosstalk, especially in high-speed applications.
Innovation Solution
The implementation of a semiconductor device and package with a redistribution layer (RDL) structure that includes at least three traces passing through the space between landing pads, with landing pads and vias designed to accommodate more traces by optimizing their shape and aspect ratio, allowing for improved signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more die-to-die signal points are incorporated into one IC die, then the functionality and pin count are improved, but the routing space in the redistribution layer is reduced and signal integrity deteriorates due to crosstalk
Solution Approach 1:
The patent transitions from a conventional planar RDL layout to a 3D stacked architecture with multiple RDL layers (first RDL, second RDL, third RDL) positioned at different heights. This vertical dimensionality allows signal traces to be routed in multiple layers, separating conflicting signals in the vertical direction and reducing crosstalk while accommodating more die-to-die signal points.
Solution Approach 2:
The redistribution layer is segmented into multiple distinct layers (first RDL, second RDL, third RDL), each handling specific signal routing functions. This segmentation distributes the routing burden across multiple layers, allowing more signal points to be accommodated without overwhelming a single planar layer, thereby maintaining signal integrity.
2Productivity
If more signal traces are arranged between landing pads, then the routing capacity is improved, but the space between landing pads must be reduced which increases manufacturing complexity
Solution Approach 1:
Instead of increasing trace density in a single planar layer which would reduce spacing requirements, the patent distributes traces across multiple vertical layers. This allows each layer to maintain adequate spacing between traces and landing pads while the aggregate routing capacity across all layers increases significantly.
Solution Approach 2:
The routing capacity is segmented across multiple RDL layers, with each layer handling a portion of the total signal traces. This segmentation allows each individual layer to be manufactured with standard precision tolerances while the cumulative effect provides high routing capacity.
3Reliability
If shielding traces are added to reduce crosstalk, then the signal integrity is improved, but the available routing space is further reduced
Solution Approach 1:
The patent provides inherent crosstalk reduction through vertical separation of signals in multiple layers, eliminating the need for additional shielding traces in the planar direction. The third RDL layer positioned above the second RDL acts as a natural shield by providing vertical spacing between signal traces, reducing crosstalk without consuming lateral routing space.
Data Source
AI summary
An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.