RDL Substrate Partial Via Interconnect for Miniaturization
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
The proposed solution involves a semiconductor device structure with a substrate having conductive and dielectric layers, including a redistribution layer (RDL) substrate with full and partial vias, and an encapsulant to protect and electrically connect an electronic device, allowing for miniaturization and efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor packages are used, then manufacturing is simpler, but package size is too large
Solution Approach 1:
The patent transitions from planar 2D interconnect layouts to 3D vertical stacking with multiple conductive layers and vias. The RDL substrate incorporates conductive layers at different heights (first conductive layer, second conductive layer, third conductive layer) connected through vias and via plugs, enabling three-dimensional signal routing that reduces package footprint while maintaining connectivity functionality.
Solution Approach 2:
The patent implements nested conductive structures where via plugs are embedded within vias, and multiple conductive layers are stacked vertically within a compact substrate volume. The first conductive layer is positioned within vias that extend through the substrate, while the second and third conductive layers are nested at different vertical levels, creating a space-efficient nested architecture that minimizes package size.
2Reliability
If conventional semiconductor packages are used, then manufacturing process is simpler, but reliability is decreased
Solution Approach 1:
The patent forms via plugs within vias before completing the final conductive layer deposition. The via plugs are prepared in advance with appropriate materials (such as copper or aluminum), and subsequent conductive layers are deposited over these pre-formed plugs. This preliminary preparation ensures proper electrical connectivity and mechanical stability are established before final assembly, improving reliability while maintaining manufacturing feasibility through standardized sequential processing steps.
3Productivity
If conventional semiconductor packages are used, then manufacturing cost is lower, but performance is reduced
Solution Approach 1:
The patent divides the interconnect structure into distinct functional segments: via plugs for vertical connections, multiple conductive layers (first, second, third conductive layers) for signal routing at different levels, and dielectric layers for insulation. Each segment performs a specific function, allowing independent optimization of signal integrity, power distribution, and grounding paths, thereby enhancing overall device performance through modular interconnect architecture.
Data Source
AI summary
In one example, a semiconductor device comprises a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture, an electronic device having an interconnect electrically coupled to the first conductor, and an encapsulant on a top side of the substrate contacting a side of the electronic device. Other examples and related methods are also disclosed herein.