Integrated RDL Test Pad Structure to Protect DRAM Top Metal
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Solution Overview
Problem
In the field of Dynamic Random Access Memory (DRAM), the top metal layer connected to the Re-Distribution Layer (RDL) is prone to damage during Wafer Acceptance Testing (WAT), leading to a decrease in yield, and the limited space in DRAM makes it difficult to apply a large RDL.
Innovation Solution
A semiconductor structure is developed, comprising a substrate, a conductive pattern layer, a support layer with a via hole, and an RDL with a test pad that includes alternately arranged test contact portions and recesses, allowing for effective electrical testing without damaging the conductive pattern layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a top metal layer connected to the RDL is used for testing, then electrical testing can be performed, but the top metal layer is easy to be damaged during Wafer Acceptance Testing
Solution Approach 1:
The patent extracts the test pad function from the top metal layer by creating a separate test pad structure within the via hole. The test pad is formed as an independent conductive structure that can be contacted separately from the top metal layer, allowing testing to be performed without applying stress to the top metal layer during WAT processes.
Solution Approach 2:
The patent introduces an intermediary test pad structure that mediates between the testing process and the top metal layer. The test pad serves as an intermediate contact point that transfers test signals to the underlying conductive layers through the via hole, eliminating the need to directly contact the top metal layer during testing.
2Reliability
If a large RDL is used for testing, then comprehensive electrical testing can be performed, but there is limited space in the DRAM
Solution Approach 1:
The patent utilizes the vertical dimension by forming the test pad within the via hole structure, extending in the depth direction rather than requiring additional lateral space. This three-dimensional arrangement allows the test pad to access conductive layers at different depths without occupying extra planar area on the DRAM chip surface.
Solution Approach 2:
The test pad is nested within the via hole structure, utilizing the existing via hole space that would otherwise be empty or filled with standard via material. This nested arrangement allows the test pad to be accommodated within the existing via hole footprint, effectively using unused vertical space without increasing the overall device area.
Data Source
AI summary
A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.