RDL Top Shape Curvature for Void Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor integrated circuits, the geometrical size of interconnect structures decreases, leading to increased IC density and device performance, but smaller process geometries result in defects like voids between redistribution layer (RDL) structures, which weaken mechanical strength and affect electrical properties, causing a high chip rejection rate and yield sensitivity to trench-filling processes.
Innovation Solution
A rounded shape is formed for the top portion of the RDL structure using a strained passivation layer and/or a mask layer trimming, which reduces defects during trench-filling processes and improves step coverage of subsequent protective layers, achieved through a combination of deposition and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the geometrical size of interconnect structures is decreased, then IC density and device performance are improved, but voids and defects occur between RDL structures, weakening mechanical strength and affecting electrical properties
Solution Approach 1:
The patent applies curvature by forming a rounded top portion on the RDL structure instead of a sharp edge. This rounded geometry reduces stress concentration and prevents void formation during trench-filling processes, thereby maintaining mechanical strength and electrical properties while enabling smaller process geometries for higher IC density
2Productivity
If the geometrical size of interconnect structures is decreased, then IC density is improved, but manufacturing precision becomes more sensitive to trench-filling processes, causing high chip rejection rate
Solution Approach 1:
The rounded top portion geometry facilitates better trench-filling processes by eliminating sharp edges that cause void formation. This curvature improvement enhances manufacturing precision and reduces chip rejection rates associated with defective trench-filling in smaller process geometries
3Ease of manufacture
If a sharp edge is formed for the RDL structure, then fabrication is simpler, but defects like voids occur during trench-filling processes, reducing production yield
Solution Approach 1:
The patent forms a rounded top portion on the RDL structure that eliminates sharp edges, thereby preventing void formation during trench-filling processes. This geometric modification improves production yield by reducing defects while maintaining ease of manufacture through standard deposition and etching processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The rounded shape of the RDL structure enhances the mechanical strength and electrical properties of the IC devices by reducing voids and defects, improving production yield and reducing manufacturing costs by ensuring proper electrical connections and preventing electrical discharge.
Implementation Method 1
a second passivation layer configured to cause stress to the PPI line
Implementation Method 2
achieved through a combination of deposition and etching processes
Implementation Method 3
achieved through a combination of deposition and etching processes
Data Source
AI summary
A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer.