RDL Trace Geometry for CTE-Stable Fan-Out Package Reliability
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Solution Overview
Problem
The increasing die size and package size in semiconductor packages lead to reliability issues due to coefficient of thermal expansion (CTE) mismatch, causing package failures such as bump cracks, mold compound delamination, and RDL failures, especially in fan-out packages with high interconnect density.
Innovation Solution
A novel redistribution layer (RDL) structure with optimized conductive trace design, featuring a V-shaped configuration with stepwise increasing widths and controlled bend angles to reduce stress, and the use of underfill and stiffener rings to manage thermal expansion and mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the die size and package size are increased to accommodate more chiplets for high-performance applications, then the interconnect density and compute power are improved, but the package stress increases due to CTE mismatch, leading to higher risk of package failures
Solution Approach 1:
The conductive trace is designed with non-uniform width, being wider at the via region and narrower at the distal end. This local variation in geometry creates a stress gradient that accommodates thermal expansion differences, with the wider via region absorbing more stress. This local quality adjustment allows the package to maintain high interconnect density while reducing overall package stress from CTE mismatch.
Solution Approach 2:
The patent changes the geometric parameters of the conductive trace, specifically the width parameter, to optimize stress distribution. By making the trace width a variable parameter rather than constant, the design can adapt to thermal stress requirements at different locations, thereby maintaining reliability while supporting larger package sizes for higher interconnect density.
2Productivity
If fine-pitch redistribution layer technology is used to enable high interconnect density, then the package footprint and performance are improved, but the package stress and risk of RDL failures increase
Solution Approach 1:
The conductive trace employs local quality variation through non-uniform width design, with the wider section at the via region specifically engineered to absorb thermal stress. This localized geometric adjustment allows fine-pitch RDL technology to achieve high interconnect density while the varying trace width compensates for the increased stress in critical regions, reducing the risk of RDL failures.
3Power
If the die size is increased to accommodate more chiplets, then the compute power and data bandwidth are improved, but the coefficient of thermal expansion mismatch causes increased package stress and potential failures
Solution Approach 1:
The patent modifies the geometric parameters of the conductive trace, specifically implementing a non-uniform width profile where the trace is wider at the via region and tapers toward the distal end. This parameter change allows larger die sizes with more chiplets for enhanced compute power, while the varying trace width accommodates thermal expansion differences, reducing package stress from CTE mismatch.
Data Source
AI summary
A redistribution layer (RDL) structure for a semiconductor package assembly is provided. The RDL structure includes a via and a first conductive trace connected to the via. The first conductive trace includes a first segment and a second segment. The first segment is disposed away from the via and extends along a first direction. The second segment is disposed close to the via and connected to the first segment. The second segment extends along a second direction. A width of the first conductive trace is stepwise increased toward the via.