Redistribution Layer Trace Routing in Semiconductor Packages
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Solution Overview
Problem
The increasing number of device-to-device interconnections in semiconductor device packages due to miniaturization and increased functionality leads to constraints on available routing area for redistribution layers (RDLs), with large capture pads occupying valuable footprint space and hindering high-density trace routing.
Innovation Solution
The implementation of semiconductor device packages with redistribution layers that omit capture pads, allowing traces to extend into dielectric openings with reduced dimensions, thereby conserving footprint area and enabling higher density interconnections between electronic devices and external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large capture pads are used to provide interconnections in RDLs, then reliable electrical connections are achieved, but valuable footprint area is occupied and high density trace routing is impeded
Solution Approach 1:
The patent removes the traditional capture pad structure from the RDL design. Instead of using large capture pads to ensure reliable connections, the invention extracts this function and replaces it with traces that extend directly into dielectric openings, thereby eliminating the area occupied by capture pads while maintaining connection reliability through the extended trace geometry
Solution Approach 2:
The patent transitions from a two-dimensional capture pad layout to a three-dimensional trace configuration that extends vertically into dielectric openings. This dimensional change allows traces to achieve better electrical contact and mechanical stability without occupying additional lateral footprint area, thus resolving the contradiction between connection reliability and area utilization
2Adaptability or versatility
If the number of device-to-device interconnections is increased to address miniaturization and increased functionality, then device functionality is enhanced, but available routing area for RDL traces is constrained
Solution Approach 1:
The patent segments the interconnection structure into multiple hierarchical levels with multiple RDL layers. By dividing the routing function across several stacked layers rather than attempting to accommodate all interconnections in a single plane, the design enables increased device functionality while managing trace density through vertical segmentation of the routing space
Solution Approach 2:
The patent utilizes the vertical dimension by implementing multiple stacked RDL layers separated by dielectric materials. This three-dimensional routing approach transforms the limited two-dimensional routing area into an expanded three-dimensional routing volume, allowing increased interconnection density without constraining the lateral footprint and enabling enhanced device functionality
Data Source
AI summary
A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.