Redistribution Layer With Variable Offset Bumps
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Solution Overview
Problem
In flip chip processing, controlled collapse chip connection (C4) solder bumps experience large stresses due to coefficient of thermal expansion (CTE) mismatches, leading to crack formation and 'white bump formation' during chip joining, especially in lead-free solder bumps, which existing redistribution layers (RDL) fail to effectively manage.
Innovation Solution
A semiconductor chip structure with a redistribution layer (RDL) featuring solder bumps that are laterally offset from their corresponding metal vias towards the center of the IC chip, with offset distances varying across the chip to mitigate stress and maintain adequate bump pitch, using a placement algorithm to determine the offset distance based on the bump's location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If C4 solder bumps are used to connect IC dies to packaging, then chip joining connections are achieved, but large stresses from CTE mismatch cause crack formation and white bump failure
Solution Approach 1:
The patent applies local quality by implementing non-uniform offset distances for solder bumps based on their specific locations on the chip. Bumps near chip edges receive larger offset distances while central bumps receive smaller offsets, creating location-specific stress compensation that addresses the CTE mismatch problem locally where it occurs most severely.
Solution Approach 2:
The patent changes the spatial parameter of bump positioning by introducing lateral offsets from the vertical alignment with underlying vias. This parameter modification alters the stress distribution characteristics, transforming the uniform stress pattern into a non-uniform pattern that compensates for edge-effect dominated CTE mismatches.
2Reliability
If solder bump size decreases to meet electromigration requirements, then current distribution improves, but stress concentration and cracking risk increase
Solution Approach 1:
The patent addresses this contradiction by applying location-dependent offset strategies. Smaller bumps at chip edges receive larger offsets to compensate for higher stress concentrations, while larger central bumps receive smaller offsets. This local differentiation maintains electromigration performance while strategically reinforcing stress vulnerability zones.
3Ease of manufacture
If uniform offset distance is applied to all solder bumps, then manufacturing simplicity is maintained, but stress compensation effectiveness is reduced due to varying bump locations
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through non-uniform offset distances that vary by bump location. The offset distance is calculated based on the bump's position relative to the chip center, with edge bumps receiving larger offsets and central bumps receiving smaller offsets, optimizing stress compensation for each location's specific stress profile.
Solution Approach 2:
The patent changes the offset distance parameter from a uniform value to a location-dependent variable. This parameter transformation enables the system to adapt the offset magnitude to the local stress conditions at each bump position, improving overall stress compensation effectiveness while maintaining a systematic implementation approach.
Data Source
AI summary
An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.