RDL Via Array Layout for Thermal Stress Relief in IC Pads

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Solution Overview

Problem

The increasing complexity of integrated circuit (IC) manufacturing due to scaling issues leads to metal filling defects in redistribution layers (RDL) caused by thermal expansion stress gradients, resulting in vacancies and voids that can disconnect signal routing vias, reducing component reliability.

Innovation Solution

Incorporating a via array in the bond pad portion with sacrificial vias surrounding a block via, which absorbs stress-caused voiding and defects, thereby reducing the risk of signal routing via breakage and maintaining circuit integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a larger bulk metal RDL pad is formed together with a smaller and thinner via, then the thermal stress is spread around the die, but metal filling issues occur in the smaller via due to stress gradients causing defects and vacancies

Engineering Contradiction:

Improvecomponent reliabilityVSAvoidvia filling quality

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The bond pad portion is segmented into multiple vias (via array) instead of a single large via. This segmentation distributes the stress and prevents vacancy aggregation that would occur in a single large via, while maintaining adequate metal filling in each smaller via.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the RDL structure are given different via configurations. The bond pad portion has a via array with multiple vias to handle stress, while the signal routing portion has fewer or no vias to maintain signal integrity. Each region's via structure is optimized for its specific functional requirements.

Inventive Principle:

Principle #3Local quality

2Stress or pressure

If a larger bulk metal RDL pad is used, then thermal stress is alleviated, but the stress gradient drives vacancy aggregation and void nucleation in the via portions

Engineering Contradiction:

Improvethermal stressVSAvoidvia connection reliability

Core Design Contradiction:

Stress or pressureVSReliability

Solution Approach 1:

The bulk metal bond pad is segmented into multiple vias arranged in an array. This segmentation creates multiple stress distribution paths and prevents the formation of large continuous stress gradients that would drive vacancy aggregation in a single large via structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The via array acts as an intermediary structure between the large bond pad and the thinner signal routing vias. It provides a transition zone that manages stress gradients and prevents direct stress transmission that would cause void nucleation in the signal routing portion.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Stress or pressure

If a larger bulk metal portion is formed, then thermal expansion stress is distributed, but the stress pulls the via portions upwards causing pull back break and disconnection

Engineering Contradiction:

Improvethermal expansion stressVSAvoidvia connection strength

Core Design Contradiction:

Stress or pressureVSStrength

Solution Approach 1:

The bond pad metal is segmented into multiple vias rather than a single large bulk metal portion. This segmentation reduces the upward pull force on any single via and distributes the thermal expansion stress across multiple connection points, preventing pull-back break.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The via array in the bond pad portion provides localized stress management where needed, while the signal routing portion maintains via structures optimized for electrical connection strength. Each region's via configuration is tailored to its specific mechanical and electrical requirements.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed RDL structure effectively alleviates stress and prevents vacancy accumulation in signal routing vias, enhancing the reliability of IC components by absorbing stress-induced defects and voids, thus maintaining continuous signal paths.

Implementation Method 1

The metal filling issues can be caused by stresses due to differences in the thermal expansion coefficients of the metal (e.g., copper) and surrounding dielectric materials

Methodology Applied

Scientific EffectThermal expansion stress: Thermal Expansion

Implementation Method 2

the stress gradient leads to vacancy aggregation and void nucleation to balance the stress in the metal

Methodology Applied

Scientific EffectVacancy aggregation and void nucleation: Nucleation

Data Source

PatentUS20250015007A1Via array in a redistribution layer structure for stress relief

Publication Date: 2025.01.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.