Redistribution Layer Via-Trace Contact Design
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Solution Overview
Problem
The semiconductor industry faces challenges in forming efficient redistribution layer (RDL) structures during packaging, particularly in achieving good contact and conductive properties between vias and traces, which can lead to high resistance and misalignment issues due to slim trace widths and adverse ultra-fine spaces.
Innovation Solution
The formation of RDL structures involves creating vias and traces with specific dimensions and arrangements, where the via width is larger than the trace width, allowing for a larger contact area and avoiding the need to widen the mask pattern, thus preventing collapse and misalignment, and using multiple layers of dielectric and redistribution layers to ensure electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the trace width is reduced to achieve higher integration density, then more components can be integrated into a given area, but the contact area between via and trace decreases leading to high resistance and misalignment issues
Solution Approach 1:
The patent transitions from two-dimensional trace patterns to three-dimensional stacked RDL structures. Multiple RDL layers are formed vertically, allowing traces to be routed in different planes. This vertical stacking enables higher integration density while maintaining adequate via-trace contact area in each layer, thereby resolving the contradiction between density and contact quality.
Solution Approach 2:
The patent divides the redistribution function into multiple separate RDL layers. Each RDL layer contains its own set of traces and vias, segmenting the complex interconnect function into manageable stages. This segmentation allows each layer to be optimized independently for both density and contact quality, with intermediate buffering layers providing mechanical and electrical stability.
2Reliability
If the via width is increased to improve contact area, then conductive properties improve, but the mask pattern must be widened which causes misalignment with slim traces
Solution Approach 1:
The patent uses vertical stacking of multiple RDL layers to provide additional contact opportunities. Instead of relying on a single large via, multiple smaller vias across different layers provide cumulative contact area, maintaining conductive properties while keeping individual via dimensions compatible with slim trace widths and standard mask patterns.
Solution Approach 2:
The patent applies different via dimensions and configurations to different locations within the same RDL layer. Via width, length, and spacing are locally optimized based on the specific trace geometry and electrical requirements at each position, allowing good contact quality without requiring uniform mask pattern widening that would cause misalignment.
3Reliability
If multiple RDL layers with buffering layers are formed, then electrical connectivity and reliability are improved, but the device complexity increases
Solution Approach 1:
The buffering layers serve multiple functions simultaneously: they provide mechanical support for subsequent RDL layers, establish electrical connections between different RDL layers, and offer pathways for signal and power distribution. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity while improving electrical connectivity.
Solution Approach 2:
The patent combines the support function and electrical connection function into the same buffering layer structures. Rather than having separate mechanical support layers and separate interconnect layers, the buffering layers perform both roles, merging multiple functions into unified structures that reduce overall device complexity.
Data Source
AI summary
A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a dielectric layer, a first redistribution layer (RDL) and a second RDL. The encapsulant laterally encapsulates the die. The dielectric layer is located on the encapsulant and the die. The first RDL penetrates through the dielectric layer to connect to the die. The second RDL is located on the first RDL and the dielectric layer. The second RDL and the first RDL share a common seed layer.