Redistribution Layer Width Variation for Thermal Stress Mitigation
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging techniques due to high bending stresses at the semiconductor-encapsulant boundary caused by coefficient of thermal expansion (CTE) mismatch, leading to potential RDL cracking and manufacturing defects in Package-on-Package (PoP) technology.
Innovation Solution
A redistribution layer (RDL) routing design is implemented with wider conductive lines over the encapsulant and integrated circuit dies near the boundary to mitigate stress, featuring varying widths and angles to accommodate CTE mismatch, thereby reducing the likelihood of cracking and manufacturing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RDL routing with uniform width is used, then manufacturing process is simple, but high bending stresses occur at the semiconductor-encapsulant boundary due to CTE mismatch causing RDL cracking
Solution Approach 1:
The RDL routing design implements varying line widths at different locations: wider conductive lines are used specifically at the semiconductor-encapsulant boundary region where CTE mismatch causes high bending stresses, while narrower lines are used in regions away from the boundary. This local variation in geometry optimizes stress distribution without unnecessarily increasing complexity throughout the entire RDL structure.
Solution Approach 2:
The invention changes the geometric parameters of the conductive lines by varying their widths and angles according to their position relative to the semiconductor-encapsulant boundary. Lines near the boundary have larger widths and specific angle configurations to accommodate thermal stresses, while lines away from the boundary use standard dimensions, thereby adapting the RDL structure to local stress conditions.
2Reliability
If wider conductive lines are used at the boundary to reduce stress, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The varying width design concentrates the manufacturing precision requirements specifically at the boundary region where wider lines are needed for stress mitigation, while standard-width lines in other regions maintain conventional precision tolerances. This localized approach to quality control reduces the overall manufacturing complexity compared to uniformly high precision requirements across the entire RDL.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances reliability robustness and reduces manufacturing defects by managing thermal stresses across the semiconductor-encapsulant boundary, ensuring more reliable and robust semiconductor package structures.
Implementation Method 1
high bending stresses at the semiconductor-encapsulant boundary caused by coefficient of thermal expansion (CTE) mismatch
Data Source
AI summary
An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, a conductive line electrically connecting a first conductive via to a second conductive via, the conductive line including a first segment over the first integrated circuit die and having a first width, and a second segment over the first integrated circuit die having a second width larger than the first width, the second segment extending over a first boundary between the first integrated circuit die and the encapsulant.