RDL Wire Segmentation for Through-Via Stress Distribution

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in reducing layout area and increasing layout flexibility in three-dimensional integrated circuits due to cracking issues in re-distribution layers (RDLs) connected to through-vias, which affect the reliability and efficiency of signal transmission.

Innovation Solution

The use of RDL wires with specific connecting patterns and shapes, such as circular or elliptical patterns, on the edges of through-vias, along with taper portions and cap portions, to distribute stress and prevent cracking, while maintaining electrical connectivity and signal transmission efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If through-vias are used to connect stacked chips or wafers in three-dimensional integrated circuits, then integration density and efficiency are improved, but cracking issues occur in re-distribution layers (RDLs) connected to through-vias

Engineering Contradiction:
Improveintegration densityVSAvoidRDL cracking resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The RDL wire is segmented into multiple portions: a first portion extending across the through-via, a second portion extending from the first portion, and a connecting pattern connecting these portions. This segmentation allows the RDL to accommodate stress around the through-via while maintaining electrical connectivity, thereby preventing cracking and improving reliability without sacrificing integration density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The connecting pattern is specifically designed with different geometries (circular, elliptical, or rectangular) to provide enhanced stress distribution at the critical location where the RDL wire crosses the through-via. This local structural modification maintains the overall RDL functionality while addressing the specific cracking issue at the via intersection point.

Inventive Principle:
Principle #3Local quality

2Reliability

If RDL wires are extended across through-vias to maintain connectivity, then electrical connectivity is maintained, but stress concentration occurs leading to cracking

Engineering Contradiction:
Improveelectrical connectivityVSAvoidRDL wire strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The connecting pattern can be designed with circular or elliptical geometries, which provide smoother stress distribution compared to sharp corners. The curved shape of the connecting pattern reduces stress concentration at the via edges, allowing the RDL wire to maintain electrical connectivity across the through-via while preventing cracking that would compromise strength.

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Ease of manufacture

If conventional RDL wire configurations are used for simplicity, then manufacturing is easier, but layout flexibility is reduced due to cracking issues

Engineering Contradiction:
ImproveRDL wire fabricationVSAvoidlayout flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The connecting pattern can be configured in different geometries (circular, elliptical, rectangular) and dimensions to accommodate various layout requirements. This parameter variability allows the RDL structure to adapt to different design needs and stress conditions while maintaining a relatively simple fabrication process, thus improving layout flexibility without significantly complicating manufacturing.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10204863B2Semiconductor package structure
Publication Date: 2019.02.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10204863B2 patent drawing
  • US10204863B2 patent drawing
  • US10204863B2 patent drawing

AI summary

Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, and a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and electrically separated from the through-via. The second surface is opposite to the first surface. A portion of the first RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.