Low Latency RDMA Architecture for High Availability Failover

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Financial trading platforms face challenges with high geographic and processing latency, as well as failures in primary systems leading to data loss and system unavailability due to the lack of low fault tolerance, necessitating advancements in computer architectures for improved latency and availability.

Innovation Solution

A transaction system architecture with a primary and secondary host setup, utilizing shared memory and remote direct memory access (RDMA) for low latency and high availability, where the secondary host can seamlessly take over in case of primary host failure, ensuring minimal data loss and rapid recovery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a primary-backup system architecture is implemented for high availability, then system reliability is improved, but failover time and data loss increase

Engineering Contradiction:
Improvesystem availabilityVSAvoidfailover time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by continuously maintaining a synchronized backup system that is pre-configured and ready to take over immediately upon primary system failure. The backup system maintains real-time synchronization with the primary system through shared memory and RDMA connections, so that when failover is triggered, the backup can assume the primary role without significant delay or data loss.

Inventive Principle:
Principle #10Preliminary action

2Speed

If geographic redundancy is implemented to reduce latency, then system responsiveness is improved, but system complexity increases

Engineering Contradiction:
Improvemessage processing speedVSAvoidsystem architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges the primary and backup systems into a unified architecture using shared memory and RDMA technology. This allows both systems to access the same data structures in memory simultaneously, eliminating the need for complex data replication protocols and synchronization mechanisms while achieving low-latency access to transaction data from either location.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If continuous data synchronization is maintained between primary and backup systems, then data integrity is improved, but processing latency increases

Engineering Contradiction:
Improvedata integrityVSAvoidsynchronization latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces traditional mechanical data synchronization methods (such as periodic data copying, network protocol exchanges, and disk-based replication) with direct memory access through RDMA technology. This allows the backup system to read transaction data directly from the primary system's memory space without involving operating system kernels, network protocol stacks, or disk I/O operations, thereby achieving near-instantaneous synchronization with minimal latency.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10360118B2Low latency system having high availability computer architecture
Publication Date: 2019.07.23 CBOE EXCHANGE INC
  • US10360118B2 patent drawing
  • US10360118B2 patent drawing
  • US10360118B2 patent drawing

AI summary

A system is disclosed for processing external inbound messages with failover protection having low latency and high availability. The system includes a primary data processing host and a secondary data processing host. Each of the primary and secondary data processing hosts include a memory space shared by separate data processing components. The memory spaces of the primary and secondary data processing hosts are synchronized using a low-latency remote direct memory access. The synchronization is performed on data items stored in the memory spaces associated with one inbound message at a time.