RDMA-SSD Unified Controller for Low-Latency Storage
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Solution Overview
Problem
Conventional network storage systems face challenges with high latency and low throughput due to the serial command/data interfaces of flash memory devices, which are power-intensive and generate heat, and suffer from longer write latency compared to read latency, making them unsuitable for enterprise storage systems where low latency and high throughput are required.
Innovation Solution
The implementation of a storage network architecture using RDMA-SSD clusters on blades with cross-over connections for high-density storage, low latency, and high IOPs, featuring unified memory and network controllers with DDR4-AFA controllers, dynamic random-access memory, and magnetoresistive random-access memory for caching, enabling low-latency zero-copy network data transfers without the need for gateway host memory hopping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional serial command/data interfaces are used to access flash memory devices, then the interface is simple to implement, but the access speed is slow and latency is high
Solution Approach 1:
The patent replaces conventional serial command/data interfaces with parallel PCIe (PCI Express) interfaces. This substitution transitions from a serial communication mechanism to a parallel communication mechanism, enabling significantly higher data transfer rates and lower latency while maintaining implementation feasibility through standardized PCIe protocols and controllers.
2Use of energy by stationary object
If flash memory devices are accessed through conventional periphery ports, then the implementation is straightforward, but power consumption is high and heat generation is substantial
Solution Approach 1:
The patent implements dynamic power management for flash memory devices accessed through PCIe interfaces. The system can dynamically adjust power states (active, idle, sleep) based on access patterns and workload demands, reducing overall power consumption while maintaining ease of access through standardized PCIe power management protocols and automatic state transitions.
3Speed
If flash memory is used for storage, then read performance is superior to hard disk drives, but write latency is 16 times longer than read time
Solution Approach 1:
The patent introduces DRAM (dynamic random-access memory) as an intermediary caching layer between the PCIe interface and flash memory devices. This mediator buffer stores frequently accessed data and write buffers, allowing read operations to be served from the fast DRAM cache and write operations to be buffered in DRAM before being asynchronously written to flash memory, thereby reducing both read latency and write latency while preserving superior read performance.
4Loss of time
If conventional SSD storage servers are used, then data access is possible, but gateway host memory hopping is required which increases latency
Solution Approach 1:
The patent extracts the memory buffering and data caching functions from the gateway host system and relocates them directly to the PCIe flash memory devices. Each flash memory device incorporates its own DRAM buffer memory and caching mechanisms, eliminating the need for data to hop through gateway host memory. This extraction of memory functions to the device level directly reduces access latency while the standardized PCIe interface maintains operational simplicity.
Data Source
AI summary
System and method for a unified memory and network controller for an all-flash array (AFA) storage blade in a distributed flash storage clusters over a fabric network. The unified memory and network controller has 3-way control functions including unified memory buses to cache memories and DDR4-AFA controllers, a dual-port PCIE interconnection to two host processors of gateway clusters, and four switch fabric ports for interconnections with peer controllers (e.g., AFA blades and/or chassis) in the distributed flash storage network. The AFA storage blade includes dynamic random-access memory (DRAM) and magnetoresistive random-access memory (MRAM) configured as data read/write cache buffers, and flash memory DIMM devices as primary storage. Remote data memory access (RDMA) for clients via the data caching buffers is enabled and controlled by the host processor interconnection(s), the switch fabric ports, and a unified memory bus from the unified controller to the data buffer and the flash SSDs.