Re-Etched RDL Seed Layers for Fine-Pitch InFO Packaging

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Solution Overview

Problem

Conventional semiconductor packaging technologies face challenges in increasing the number of I/O pads on smaller die sizes due to limited pitch and solder ball size constraints, leading to issues like solder bridges and reduced packaging efficiency.

Innovation Solution

The implementation of an Integrated Fan-Out (InFO) package with a three-step etching process to form redistribution lines (RDLs) that reduces undercuts in metal vias and lines, enhancing their reliability and allowing for increased I/O pad density without compromising structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional packaging technology is used with limited pitch, then manufacturing simplicity is maintained, but I/O pad density is limited and solder bridges occur

Engineering Contradiction:
ImproveI/O pad densityVSAvoidpitch control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent transitions from planar 2D packaging to 3D vertical packaging by forming stacked die structures with multiple layers of I/O pads connected through vertical vias. This dimensional change allows significantly higher I/O pad density without reducing the pitch on individual die surfaces, thereby avoiding solder bridges while increasing the quantity of I/O pads.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested packaging by stacking multiple die layers vertically, where each die is positioned over the previous layer and connected through alignment marks and vias. This nesting approach enables multiple I/O interfaces to be packed in a compact vertical space, dramatically increasing I/O pad density without compromising pitch control on each die layer.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If fan-out packages are implemented to increase I/O pad area, then I/O pad density improves, but manufacturing complexity increases due to additional etching steps

Engineering Contradiction:
ImproveI/O pad densityVSAvoidetching process steps
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The etching process is segmented into distinct selective steps: first etching through the first dielectric layer to form vias, then etching through the second dielectric layer to form additional vias and trenches. This segmentation allows precise control over the formation of RDL structures at different vertical levels, enabling complex 3D interconnects while managing process complexity through systematic step-by-step fabrication.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by using different etching selectivities for different dielectric layers and regions. The first and second dielectric layers have different etching rates, allowing selective removal of material in specific areas to form vias, trenches, and RDL structures. This localized control enables precise formation of interconnect structures without requiring excessive process steps.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If undercut formation occurs in RDLs, then manufacturing simplicity is maintained, but reliability of fine-pitch RDLs deteriorates

Engineering Contradiction:
ImproveRDL formation simplicityVSAvoidfine-pitch RDL reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by forming a mandrel structure before depositing the RDL material. The mandrel serves as a template that defines the precise geometry of the RDL, preventing undercut formation during subsequent etching or deposition processes. This preliminary structure ensures that fine-pitch RDLs maintain their intended dimensions and profiles, thereby improving reliability while keeping the manufacturing process manageable.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent performs preliminary actions by first forming vias and trenches through selective etching, then filling these structures with conductive material to form RDLs. This sequence of preliminary actions ensures that the RDLs are formed in precisely defined locations with controlled dimensions, preventing undercut issues and ensuring reliability of fine-pitch interconnects before subsequent packaging steps are performed.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The three-step etching process improves the reliability of RDLs by eliminating or reducing undercuts, enabling higher I/O pad density and packaging efficiency, particularly for fine-pitch RDLs, while maintaining cost-effectiveness by selectively applying the process only where necessary.

Implementation Method 1

performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS11742317B2Process including a re-etching process for forming a semiconductor structure
Publication Date: 2023.08.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11742317B2 patent drawing
  • US11742317B2 patent drawing
  • US11742317B2 patent drawing

AI summary

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.