RE Mapper Functional Split Using PRB Control Grids

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Solution Overview

Problem

The existing implementation of the Resource Element (RE) mapper in heterogeneous computing systems requires excessive programmable logic resources and processing time due to complex control information handling, leading to underutilization of processing systems and increased latency.

Innovation Solution

A system and method that split the RE mapping process between a processing system and programmable logic, utilizing Direct Memory Access (DMA) to transfer pre-processed control information per Physical Resource Block (PRB) from the processing system to the programmable logic, reducing the need for additional programmable logic resources and processing cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the RE mapper processes control information for all downlink physical chains in the programmable logic (PL), then the mapping function is completed, but the PL resources and processing cycles are excessively consumed

Engineering Contradiction:
ImproveRE mapping function completionVSAvoidprogrammable logic resources
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the RE mapping process into two parts: control information processing is separated from data mapping. The processing system handles control information generation and preparation, while the PL focuses only on the actual mapping operation. This segmentation reduces PL resource consumption by eliminating the need for PL to process control information.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts the control information processing function from the PL and relocates it to the processing system. By taking out this non-critical function, the PL's resource burden is reduced, allowing it to dedicate resources solely to the time-critical mapping operation.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If the RE mapper waits for data processing of all downlink physical chains to complete before processing control configuration, then data integrity is maintained, but the processing system remains underutilized and latency increases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by having the processing system generate and prepare control information in advance (in slot N-1), before the actual mapping operation is needed in slot N. This advance preparation eliminates waiting time and allows the PL to immediately perform mapping when data is ready, reducing latency while maintaining data integrity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous useful action by allowing the processing system to work continuously on control information generation without idle waiting periods. The PL also maintains continuous operation by receiving pre-prepared control information and immediately processing it, eliminating gaps in the workflow.

Inventive Principle:
Principle #20Continuity of useful action

3Manufacturing precision

If control parameters of each channel are processed to map processed data onto slot grid, then accurate mapping is achieved, but the RE mapper design complexity increases

Engineering Contradiction:
Improvemapping accuracyVSAvoidRE mapper design complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the mapping process into control information generation (processing system) and mapping execution (PL). By separating these functions, the PL's design complexity is reduced as it only needs to handle the mapping logic, while the processing system handles the complex control parameter processing and grid arrangement.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250393030A1System and method for efficient re-(DE)mapper design in heterogeneous computing system
Publication Date: 2025.12.25 JIO PLATFORMS LTD
  • US20250393030A1 patent drawing
  • US20250393030A1 patent drawing
  • US20250393030A1 patent drawing

AI summary

The present disclosure provides a system and a method for controlling overhead and functional split of a Resource Element (RE) mapper in a heterogeneous system. The system may receive physical channel Protocol Data Units (PDUs) including one or more parameters. The system may pre-process the one or more parameters of the physical channel PDUs. and generate one or more bits of control information per Physical Resource Block (PRB) based on the pre-processed one or more parameters. The system may arrange the generated one or more bits of control information per PRB in a grid, and transfer the grid including the generated one or more bits of control information per PRB from a processing system to a programmable logic of the heterogeneous system using a Direct Memory Access (DMA). The RE mapper in programmable logic space uses control grid to arrange/map data of various physical channels for over the air transmission.