Reactive Droop Limiter Using Clock Pulse Removal
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Solution Overview
Problem
Voltage droop in processors can lead to timing failures and reduced power efficiency due to sudden changes in effective switched capacitance and clock frequency, with existing solutions unable to rapidly mitigate the initial 70% droop occurring within 15 ns.
Innovation Solution
A method and apparatus that detect voltage droop by measuring clock edge position changes or voltage directly, and respond by reducing the frequency of the clock signal through a frequency divider, thereby mitigating the droop by removing a proportion of clock pulses to increase VDD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve processor performance, then productivity is improved, but voltage droop occurs due to increased effective switched capacitance
Solution Approach 1:
The system proactively monitors voltage levels and predicts impending droop conditions before they occur. By detecting trends in voltage degradation and correlating them with clock frequency and effective switched capacitance changes, the system takes preliminary action to adjust voltage or frequency before the droop becomes severe enough to cause timing failures.
Solution Approach 2:
The system continuously monitors voltage droop conditions and uses this feedback to dynamically adjust processor operation. The monitoring circuit measures actual voltage levels, and this information feeds back to control logic that can reduce clock frequency or trigger voltage regulation adjustments, creating a closed-loop system that maintains voltage stability while maximizing performance.
2Reliability
If the power supply voltage is increased to compensate for droop, then voltage stability is improved, but power efficiency deteriorates
Solution Approach 1:
The system dynamically adjusts the processor clock frequency in real-time based on monitored voltage conditions and effective switched capacitance changes. Rather than maintaining a fixed high voltage that would waste power during low-stress periods, the frequency is adaptively reduced only when and where voltage droop threatens timing margins, optimizing the balance between performance and power efficiency.
Solution Approach 2:
The system changes operational parameters (clock frequency, voltage thresholds) based on real-time conditions. By monitoring effective switched capacitance and voltage levels, the system adjusts the clock frequency to match actual processing needs and voltage capabilities, avoiding unnecessary power consumption while maintaining adequate performance headroom.
3Reliability
If the response time of the power controller is reduced to mitigate early droop, then voltage stability is improved, but device complexity increases
Solution Approach 1:
The system uses the processor's own operational characteristics (clock frequency, effective switched capacitance) and existing voltage monitoring infrastructure to detect and respond to droop conditions. Rather than requiring an entirely external control system, the processor essentially monitors and adjusts itself, leveraging its inherent signals and structures to achieve rapid response without proportionally increasing overall system complexity.
Data Source
AI summary
During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider that is configured to receive an output of a clock signal generator (e.g. a phase locked loop) and produce an output signal in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way (as may be understood by examining equation 3) VDD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive VDD droop across the processor.