Reactive Initialization Formal Verification Logic Design
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Solution Overview
Problem
Traditional chip verification methods, such as simulation, become increasingly difficult and time-consuming due to the growing complexity of integrated circuits, and existing formal verification tools often provide inconclusive results, requiring simulation test benches and significant designer effort.
Innovation Solution
A system and method using reactive initialization to verify electronic logic designs by automatically assigning initial states and interacting with a correction-unit to provide feedback, allowing for more conclusive verification results without the need for simulation test benches, and optimizing computing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional simulation methods are used for chip verification, then verification can be performed with existing tools, but verification becomes increasingly difficult and time-consuming as circuit complexity increases
Solution Approach 1:
The patent replaces traditional simulation-based verification with formal verification methods. Instead of using simulation test benches and manual test vector development, the system uses mathematical proofs and automated formal verification engines to verify design properties, eliminating the time-consuming simulation process while maintaining verification reliability
Solution Approach 2:
The formal verification system automatically generates and executes verification proofs without requiring manual test bench development or test vector creation by designers. The system self-manages the verification process, including automatic property checking and constraint application, significantly reducing the time and skill required for verification setup
2Reliability
If formal verification is used to provide mathematical proofs of correctness, then verification reliability improves, but the process often gives only inconclusive partial pass results
Solution Approach 1:
The patent segments the verification process into distinct phases: reactive initialization phase (setting up initial state constraints), property checking phase (verifying specific properties), and constraint application phase (applying assumptions and invariants). This segmentation allows the formal verification engine to systematically tackle complex verification problems in manageable steps, improving conclusiveness while managing process complexity
Solution Approach 2:
The system performs preliminary reactive initialization by automatically establishing initial state constraints and assumptions before the actual property verification begins. This preliminary setup includes automatically generating initial state constraints and applying invariants, which prepares the verification engine to produce more conclusive results by eliminating ambiguous partial pass scenarios
3Reliability
If verification tools analyze properties starting from power-on state, then complete verification coverage is achieved, but computational resources are excessively consumed
Solution Approach 1:
The patent applies local quality by focusing verification efforts on specific reachable states and property-relevant portions of the state space rather than uniformly analyzing all possible states from power-on. The system identifies and concentrates computational resources on verifying properties in the locally relevant state space, maintaining verification coverage for critical properties while reducing overall computational consumption
4Reliability
If simulation test benches are developed to aid verification, then verification effectiveness improves, but considerable time and skill are required from designers
Solution Approach 1:
The formal verification system performs self-service by automatically generating verification configurations, applying constraints, and executing property checks without requiring manual test bench development. The system autonomously manages the entire verification setup process, eliminating the need for designer intervention in creating test vectors and test benches, thereby achieving high automation while maintaining verification effectiveness
Data Source
AI summary
A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to complete. Assigning an initial state simplifies the verification of the validity of the remaining states in the sequence, thus making it more likely to reach a conclusive result and consuming less computing resources.