Reactive Mappers for Parallel Intent Model Compilation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current network management systems face challenges in efficiently configuring and managing network devices, particularly in extending unified intent models and compiling low-level configuration data, which can lead to performance issues and inefficiencies in handling changes and updates.
Innovation Solution
A network management system that uses reactive mappers to support parallel and incremental compilation of unified intent models, allowing for extensibility and tracking translations, enabling the same mapper to handle create, update, and delete scenarios, and triggering deployments once all translations are completed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial compilation methods are used to compile unified intent models, then the system can process configurations sequentially, but the time required for site activation and configuration updates becomes excessively long
Solution Approach 1:
The compilation process is divided into independent tasks assigned to multiple worker threads. Each worker thread processes specific vertices or edges in the intent model graph independently, allowing parallel compilation that reduces overall site activation time from sequential processing to concurrent execution.
Solution Approach 2:
The system transitions from single-threaded sequential compilation to multi-threaded parallel compilation by introducing a threading dimension to the processing architecture. This enables simultaneous execution of compilation tasks across multiple threads, dramatically reducing the time required to compile intent models and activate sites.
2Adaptability or versatility
If the unified intent model graph is extended to support new use cases, then system versatility improves, but the compilation logic becomes more complex and harder to manage
Solution Approach 1:
The compilation logic is segmented into separate, modular components - one for parsing the intent model graph, another for compiling each vertex type, and a third for generating configuration data. This modular architecture allows new use cases to be added by implementing only the relevant vertex compiler without affecting other parts of the system.
Solution Approach 2:
A universal vertex compiler framework is implemented that can handle multiple vertex types through a common interface. The compiler uses polymorphic design where base compiler logic remains unchanged while specific vertex types inherit and override only the necessary compilation methods, enabling extensibility without proportionally increasing overall system complexity.
3Manufacturing precision
If comprehensive translation mapping is provided for all intent model changes, then configuration accuracy improves, but the processing overhead and system complexity increase
Solution Approach 1:
Instead of applying a uniform translation approach to all intent model elements, the system implements localized translation logic for each vertex and edge type. Each element has its own specialized compiler method that handles its specific translation requirements, maintaining high accuracy while reducing overall processing complexity through targeted rather than blanket processing.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An example controller device manages a plurality of network devices. The controller device includes one or more processing units, implemented using digital logic circuitry, configured to receive data representing a modification to unified intent model represented by a graph model, determine one or more vertices of the graph model affected by the data representing the modification and one or more vertices to be added to the graph model to extend the unified intent model, update the one or more vertices of the graph model affected by the data representing the modification and add the one or more vertices to be added to the graph model, compile the updated one or more vertices and the added one or more vertices to generate low level configuration data for the plurality of network devices, and configure one or more of the plurality of network devices with the low level configuration data.