Read Accumulator Circuitry for Complex Logical Functions in Memory Cells
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Solution Overview
Problem
Existing memory cells can only perform simple logical functions when connected to the same read bit line, limiting the complexity of operations that can be executed across multiple memory cells.
Innovation Solution
Incorporating dual port SRAM cells with additional read circuitry that enables XOR, AND, and OR logical operations by using a read register to accumulate and combine results from multiple memory cells connected to the same read bit line, allowing for more complex logical functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional SRAM cells are used with simple read bit line circuitry, then the device complexity is low, but the computational capability is limited to simple logical functions only
Solution Approach 1:
The patent implements read accumulator circuitry that can perform multiple logical functions (AND, OR, XOR, XNOR) within the same memory cell structure. The read bit line circuitry is designed to accumulate data from multiple memory cells and perform complex logical operations, enabling a single memory cell to serve both storage and computational purposes across different operational modes.
Solution Approach 2:
The patent combines the read accumulator functionality directly within the memory cell structure by integrating read bit line circuitry that can accumulate and process data from multiple cells. This merging of storage and computation functions within the same physical structure enables complex logical operations without requiring separate processing units, thereby enhancing computational capability while controlling device complexity.
2Adaptability or versatility
If additional read circuitry is added to enable complex logical functions, then the computational capability is enhanced, but the device complexity increases
Solution Approach 1:
The read accumulator circuitry is designed to perform multiple logical functions (AND, OR, XOR, XNOR) within the same hardware structure. By making the read circuitry universal and capable of executing different logical operations through configuration rather than dedicated hardware for each function, the patent enhances logical function capability while avoiding proportional increases in device complexity.
Solution Approach 2:
The memory cells perform their own computational operations through the integrated read accumulator circuitry. The read bit line circuitry automatically accumulates and processes data from multiple memory cells during the read operation itself, eliminating the need for separate processing stages and reducing overall circuitry complexity while enhancing computational capability.
3Productivity
If multiple memory cells are connected to the same read bit line for parallel operations, then the productivity is improved, but the measurement precision of individual cell results deteriorates
Solution Approach 1:
The read accumulator circuitry acts as an intermediary between multiple memory cells and the final read output. It collects data from multiple cells connected to the same read bit line, performs the desired logical accumulation operation, and produces a single precise result. This intermediary structure enables parallel processing of multiple cells while maintaining measurement precision through controlled accumulation logic.
Solution Approach 2:
The read accumulator circuitry implements feedback mechanisms to track and manage the accumulation state from multiple memory cells. By using feedback to control the accumulation process and ensure proper logical operations are performed on the combined data, the system maintains high measurement precision even when processing multiple cells in parallel through the same read bit line.
Data Source
AI summary
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.