Read Algorithms for 3D Crosspoint Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing read algorithms for three-dimensional crosspoint memory architectures cause a spike in current through memory cells, leading to degradation of the phase change material and reduced durability of memory states, especially in crystalline PM regions, limiting the number of consecutive reads before needing a refresh write and increasing error rates.
Innovation Solution
Implementing read algorithms that ramp one address line at a time, stabilizing it before ramping the other, to reduce the voltage gradient and current spike, thereby minimizing disturbance to the crystalline PM region and enhancing read durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read algorithms are used to read memory cell states, then read speed is maintained, but current spikes cause degradation of phase change material and increased read errors
Solution Approach 1:
The patent applies preliminary action by ramping up the voltage on one address line before the other during a read operation. Specifically, the first address line voltage is ramped to a first level and held steady before ramping the second address line voltage. This sequential approach prevents simultaneous voltage application that would cause current spikes, thereby protecting the phase change material from degradation while maintaining read functionality.
2Duration of action of moving object
If conventional read algorithms are used, then read operations can be performed, but the number of consecutive reads before refresh write is limited
Solution Approach 1:
The patent applies preliminary action by ramping up the voltage on one address line before the other during a read operation. Specifically, the first address line voltage is ramped to a first level and held steady before ramping the second address line voltage. This sequential approach prevents simultaneous voltage application that would cause current spikes, thereby protecting the phase change material from degradation while maintaining read functionality.
3Productivity
If conventional read algorithms are used, then read bandwidth is achieved, but error correction latency overhead increases
Solution Approach 1:
The patent applies preliminary action by ramping up the voltage on one address line before the other during a read operation. Specifically, the first address line voltage is ramped to a first level and held steady before ramping the second address line voltage. This sequential approach prevents simultaneous voltage application that would cause current spikes, thereby protecting the phase change material from degradation while maintaining read functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the disturbance to the crystalline PM region, allowing for more consecutive reads before refresh writes are needed, lowers read errors, and decreases latency overhead due to error correction, resulting in higher read bandwidth and lower energy consumption.
Implementation Method 1
memory cells may encode different states based on the state of a phase change material in the memory cell
Implementation Method 2
Mechanisms for reading the state of these cells, which cause a spike in current through the cell
Data Source
AI summary
In one embodiment, a state is reach from a memory cell comprising a phase change material (PM) region and a select device (SD) region by: ramping a voltage applied to a first address line of an address line pair corresponding to the memory cell until the first address line voltage is stabilized at a predetermined voltage, ramping a voltage applied to a second address line of the address line pair corresponding to the memory cell, detecting a snap in the memory cell while ramping the voltage applied to the second address line, and determining a state of the memory cell based on a differential voltage between the first and second address lines when the memory cell snap occurred.