Read Assist Scheme for Reducing Memory Access Time
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Solution Overview
Problem
Existing memory technologies face challenges in reducing read access time, which is critical for high-speed memories like SRAMs, due to the time required for bit line discharge and sensing, especially as memory usage increases beyond 100 Megabits per die, leading to increased cycle time and manufacturing yield issues.
Innovation Solution
A read assist scheme is implemented using a precharge circuit and transmission gate that selectively connects bit lines to a sense circuit with a delayed control signal, allowing bit lines to discharge to a lower voltage level, thereby reducing read access time without relying on complete discharge, and incorporating a feedback circuit to maintain bit line voltage during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional read circuits are used with standard bit line discharge methods, then the circuit structure remains simple, but the read access time is excessive and limits memory cycle time
Solution Approach 1:
The sense amplifier input node is precharged to a voltage level higher than the bit line precharge voltage. This preliminary action creates a voltage differential that accelerates the sensing process when the transmission gate connects the bit line to the sense amplifier, reducing the time required to detect the stored data value.
Solution Approach 2:
The patent changes the voltage parameter of the sense amplifier input node by precharging it to a level higher than the bit line precharge voltage. This parameter change enables faster voltage transition detection at the sense amplifier, directly reducing read access time without requiring complete bit line discharge.
2Measurement precision
If bit lines are completely discharged to sense data, then sensing accuracy is improved, but the time required for complete discharge increases the read access time
Solution Approach 1:
Instead of waiting for complete bit line discharge to sense the data, the patent uses partial discharge detection. The sense amplifier input node is precharged to a higher voltage level, enabling it to accurately detect the data value before the bit line fully discharges. This partial action approach maintains sensing accuracy while significantly reducing the time required.
Solution Approach 2:
The patent replaces the traditional mechanical waiting process for complete bit line discharge with an electrical field-based detection method. By precharging the sense amplifier input node to a higher voltage level, the system can detect voltage transitions and sense data values during the partial discharge phase, eliminating the time penalty associated with waiting for complete discharge.
3Speed
If additional power supplies or larger die area are used to reduce read access time, then read speed is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent uses the existing precharge circuitry and voltage levels already present in the memory system to achieve faster read access. By precharging the sense amplifier input node to a higher voltage level using available power supplies, the system improves read speed without requiring additional power supply voltages or external components, thereby avoiding increased manufacturing complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces read access time by approximately 30% compared to conventional methods, improving memory cycle efficiency and manufacturing yield while avoiding the need for additional power supplies or increased die area.
Implementation Method 1
The precharge circuit is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level
Implementation Method 2
The transmission gate is operative to selectively connect a given one of the bit lines with the sense circuit during a second mode as a function of at least a second control signal
Implementation Method 3
the given one of the bit lines is discharged to at least a third voltage, the third voltage being between the first and second voltage levels
Data Source
AI summary
A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.