Read Channel ECC Overlap for Faster Sequential Track Reads
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Solution Overview
Problem
Data storage devices face inefficiencies due to reliance on track skew for postprocessing time, which is insufficient for complex encoding and error correction, leading to increased sequential track processing times.
Innovation Solution
Implementing a read/write channel circuit that enables overlapping postprocessing of data tracks by using error correction codes to process multiple tracks simultaneously, with decision-tree logic for managing head positioning and memory resources to reduce reliance on track skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If track skew is used to provide postprocessing time, then error correction processing can be completed, but sequential track processing time increases
Solution Approach 1:
The patent applies preliminary action by performing postprocessing operations on previously read tracks during the time when the read head is positioned on subsequent tracks. The channel circuit maintains buffers of previously read track data and continues processing (ECC decoding, interleaving, de-scrambling) in the background while the head moves to and reads new tracks, thus preparing data in advance rather than waiting for complete processing before proceeding.
Solution Approach 2:
The patent implements continuity of useful action by ensuring that the channel circuit never remains idle. While the read head is reading new tracks, the channel circuit continuously processes previously buffered track data through error correction decoding, interleaving, and de-scrambling operations. This overlapping of read operations with postprocessing operations eliminates idle time and maintains continuous productive work flow.
2Reliability
If complex encoding and error correction processing is performed, then data reliability improves, but processing time per track increases
Solution Approach 1:
The patent applies preliminary action by performing computationally intensive postprocessing operations (ECC decoding, interleaving, de-scrambling) on previously read tracks during the time the read head is positioned on and reading subsequent tracks. This allows error correction processing to be completed in advance before the data is needed, ensuring data integrity without delaying subsequent track processing.
Solution Approach 2:
The patent implements continuity of useful action by maintaining continuous processing throughput through overlapping operations. The channel circuit processes multiple tracks through error correction and postprocessing in parallel with ongoing read operations, ensuring that computationally intensive operations never cause idle time and maintaining high productivity while ensuring complete error correction processing.
3Manufacturing precision
If track skew time is increased to allow postprocessing completion, then processing accuracy improves, but sequential access speed decreases
Solution Approach 1:
The patent applies preliminary action by completing all postprocessing operations (ECC decoding, interleaving, de-scrambling) on previously read tracks before the data is required by the host system. The channel circuit maintains buffers of processed data and ensures complete error correction and formatting is performed in advance, guaranteeing processing accuracy without requiring extended track skew time that would reduce sequential access speed.
Solution Approach 2:
The patent implements continuity of useful action by maintaining uninterrupted processing throughput. The channel circuit continuously performs postprocessing operations on buffered data from previous tracks while simultaneously reading new tracks, ensuring that processing accuracy is maintained through complete error correction while sequential access speed remains high due to eliminated idle time between tracks.
Data Source
AI summary
Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.