Read-Circuit FET Crystal Orientation for Low-Noise Imaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Imaging devices face challenges in reducing noise, particularly 1/f noise, due to interface states in field effect transistors, which affect the performance and accuracy of signal processing.
Innovation Solution
The imaging device incorporates a field effect transistor with a semiconductor layer having a (100) crystal plane orientation for its main, first, and second side surfaces, where the gate electrode covers these surfaces via a gate insulating film, reducing interface states and trapped electric charges, thereby minimizing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional field effect transistor structure is used in the read circuit, then the device complexity is reduced and manufacturing is easier, but interface states form at the semiconductor-gate insulating film boundary, causing trapped electric charges and increasing noise (particularly 1/f noise)
Solution Approach 1:
The patent applies local quality by specifying that the semiconductor layer must have a (100) crystal plane orientation at the interface with the gate insulating film. This local crystallographic property reduces interface states and trapped charges at the critical semiconductor-gate insulator boundary, thereby reducing noise without requiring fundamental changes to the overall transistor structure
Solution Approach 2:
The patent changes the crystal orientation parameter of the semiconductor layer from conventional orientations (such as <110>) to specifically <100>. This parameter change in crystal structure fundamentally alters the interface properties, reducing interface state density and associated noise while maintaining standard transistor operation
2Object-affected harmful factors
If the semiconductor layer crystal plane is oriented at (100), then interface states are reduced and noise is minimized, but the manufacturing precision requirements increase to maintain this specific crystal orientation throughout fabrication
Solution Approach 1:
The patent employs preliminary action by establishing the (100) crystal plane orientation at the semiconductor layer formation stage, before subsequent fabrication steps. This preliminary establishment of the correct crystal orientation ensures that all subsequent processing steps work with the optimal crystal structure already in place, reducing the need for complex realignment or correction procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces noise in the imaging device, allowing for improved signal processing and potentially smaller pixel sizes with increased layout flexibility.
Implementation Method 1
the field effect transistor included in the read circuit can reduce an interface state of the first side surface on which the channel is formed, and can reduce an electric charge (for example, electrons) trapped in the interface state
Data Source
AI summary
An imaging device in which noise can be reduced, and an electronic device using this device. The imaging device includes a light receiving element, and a read circuit. A field effect transistor in the read circuit has a semiconductor layer in which a channel is formed, a gate electrode that covers the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode. The semiconductor layer has a main surface, and a first side surface on one end side of the main surface in a gate width direction of the field effect transistor. The gate electrode has a first portion that faces the main surface via the gate insulating film, and a second portion that faces the first side surface via the gate insulating film. A crystal plane of the first side surface is a plane or a plane equivalent to the plane.