DRAM Read Circuit Inversion Control for Power Reduction

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Solution Overview

Problem

In the field of semiconductor memory technologies, particularly in DRAM protocols, there is a challenge to balance speed and power saving while ensuring signal integrity and data reliability during read operations.

Innovation Solution

A read operation circuit is introduced, comprising a data determination module, data receiving module, parallel-to-serial conversion circuit, data buffer module, and precharge module, which determines whether to invert read data based on the number of high bits, reducing the number of inversions on the global bus and thus lowering electric current and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data inversion is performed on the global bus to ensure signal integrity, then data transmission reliability is improved, but power consumption increases due to increased number of inversions

Engineering Contradiction:

Improvedata transmission reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies inversion strategically by determining whether to invert read data based on the number of high bits. When the number of high bits exceeds a threshold, inversion is performed to ensure signal integrity; when the threshold is not exceeded, inversion is skipped to reduce power consumption. This selective inversion approach resolves the contradiction between reliability and power consumption.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the parameter of data inversion based on the number of high bits in the read data. By using a threshold comparison on the high bit count, the system dynamically adjusts whether inversion occurs, optimizing the balance between maintaining signal integrity and reducing power consumption during data transmission.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If data inversion is performed to maintain signal integrity, then data reliability is improved, but internal bus inversion frequency increases leading to higher power consumption

Engineering Contradiction:

Improvesignal integrityVSAvoidinternal bus inversion energy loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent uses selective inversion based on high bit count threshold. When the threshold is not exceeded, the system avoids inversion entirely, preventing unnecessary internal bus inversions and associated energy losses while still maintaining signal integrity through the precharge low architecture.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent converts the potential harm of frequent inversions into a benefit by using the high bit count as a decision criterion. Instead of inverting data routinely, the system inverts only when necessary (when high bit count exceeds threshold), thereby reducing energy loss while maintaining signal integrity where needed.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Use of energy by moving object

If precharge low architecture is used to reduce power consumption, then energy efficiency is improved, but data transmission speed may be affected

Engineering Contradiction:

Improvepower consumptionVSAvoiddata transmission speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent makes the data transmission process dynamic by selectively inverting data based on real-time analysis of high bit count. This dynamic approach allows the system to adapt to different data patterns, maintaining fast transmission speeds by avoiding unnecessary inversions while still ensuring signal integrity through the precharge low architecture when needed.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11875053B2Read operation circuit, semiconductor memory, and read operation method

Publication Date: 2024.01.16 CHANGXIN MEMORY TECH INC

AI summary

Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to Low.