Hierarchical Read-Combining Cache Memory for Multicore Bandwidth
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Solution Overview
Problem
In multicore processing, multiple processing cores often request the same data from memory, leading to insufficient bandwidth and inefficient cache memory use due to the inability to rapidly fulfill all data requests simultaneously.
Innovation Solution
Implementing hierarchical read-combining cache memory, where a memory controller holds data requests for a period to aggregate multiple requests for the same data, reducing bandwidth demands and increasing cache memory efficiency by combining requests into a single read request.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple processing cores simultaneously request the same data from memory, then data retrieval speed increases, but bandwidth requirements exceed available capacity and cache memory efficiency decreases
Solution Approach 1:
The patent implements read-combining logic that merges multiple simultaneous read requests for the same data into a single memory transaction. When multiple processing cores request identical data concurrently, the system combines these requests and fetches the data once from memory, then distributes it to all requesting cores. This directly resolves the contradiction by maintaining fast data retrieval speed while reducing bandwidth consumption through request consolidation.
Solution Approach 2:
The system performs preliminary actions by holding read requests in a buffer before sending them to memory. The read-combining logic examines pending requests and aggregates them into consolidated transactions, preparing multiple requests in advance so that when memory is accessed, the data can be served efficiently to multiple cores simultaneously. This preliminary aggregation reduces the number of separate bandwidth transactions required.
2Loss of time
If the memory controller processes each data request immediately, then response time is minimized, but cache memory is not utilized efficiently and bandwidth is wasted
Solution Approach 1:
The memory controller performs preliminary examination of read requests before executing them. The read-combining logic analyzes incoming requests and identifies opportunities to aggregate multiple requests for the same data into single memory transactions. This preliminary processing maintains fast response times while significantly improving cache memory efficiency by preventing redundant reads and maximizing utilization of the memory subsystem.
Solution Approach 2:
The system implements feedback mechanisms where the memory controller monitors and tracks read requests patterns. When multiple cores request the same data concurrently, the feedback loop detects this pattern and triggers read-combining logic to aggregate the requests. This feedback-driven approach ensures that cache memory is efficiently utilized while maintaining responsive data retrieval, resolving the contradiction between response time and productivity.
Data Source
AI summary
The present disclosure relates to a system for hierarchical read-combining memory having a multicore processor operably coupled to a memory controller. The memory controller is configured for receiving a plurality of requests for data from one or more processing cores of the multicore processor, selectively holding a request for data from the plurality of requests for an undetermined or indefinite amount of time, and selectively combining a plurality of requests for the same data into a single read-combined data request. The present disclosure further relates to a method for hierarchical read-combining data requests of a multicore processor and a computer accessible medium having stored thereon computer executable instructions for performing a procedure for hierarchical read-combining data requests of a multicore processor.