Read Data Stage Circuitry for DDR-SDRAM Timing Adaptation
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Solution Overview
Problem
Mobile DDR-SDRAM memory devices exhibit significant variation in propagation delay and access time, making it challenging to operate at higher frequencies without data-read errors, as existing read data stage circuitry is not tolerant of the intrinsic timing differences between mobile and standard DDR-SDRAM devices.
Innovation Solution
A read data stage circuitry architecture that samples data every two DQS cycles, using a set of registers triggered by both edges of the delayed control signal, with multiplexers and DFFs to recirculate data and extend the clock range, allowing safe data capture across varying operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read data stage circuitry is used for mobile DDR-SDRAM devices, then the circuit can operate at standard frequencies, but data-read errors occur due to significant variation in propagation delay and access time
Solution Approach 1:
The patent implements dynamic timing adjustment by introducing a delay element that can be configured to different delay values. This delay element is controlled by a timing adjustment circuit that adapts the sampling timing based on the actual propagation delay and access time of the mobile DDR-SDRAM device, allowing the system to dynamically compensate for timing variations and prevent data-read errors
Solution Approach 2:
The patent changes the timing parameter by introducing a configurable delay element that adjusts the sampling clock phase. By modifying the delay parameter in response to detected timing variations, the system adapts to different propagation delays and access times characteristic of mobile DDR-SDRAM devices, thereby improving data-read reliability
2Productivity
If the sampling clock frequency is increased to improve data transfer rate, then productivity increases, but the circuit becomes more sensitive to propagation delay variation
Solution Approach 1:
The patent enables dynamic timing adjustment by introducing a delay element that can be configured to different delay values. This delay element is controlled by a timing adjustment circuit that adapts the sampling timing based on the actual propagation delay and access time of the mobile DDR-SDRAM device, allowing the system to dynamically compensate for timing variations and prevent data-read errors
Solution Approach 2:
The patent performs preliminary timing characterization by detecting the actual propagation delay and access time before data reading operations. The timing adjustment circuit pre-adjusts the sampling clock delay based on these detected parameters, ensuring that the sampling timing is optimized before high-speed data transfer begins, thereby maintaining reliability at higher transfer rates
3Device complexity
If a simple register-based sampling circuit is used, then device complexity is low, but the circuit cannot accommodate varying access times of mobile DDR devices
Solution Approach 1:
The patent introduces a delay element as an intermediary component between the sampling clock and the register-based sampling circuit. This delay element acts as a mediator that adjusts the timing of the sampling clock to match the varying access times of mobile DDR devices, allowing the simple register-based circuit to accommodate timing variations without increasing overall circuit complexity
Solution Approach 2:
The patent changes the timing parameter by introducing a configurable delay element that adjusts the sampling clock phase. By modifying the delay parameter in response to detected timing variations, the system adapts to different propagation delays and access times characteristic of mobile DDR-SDRAM devices, thereby improving data-read reliability
Data Source
AI summary
A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of the data bus carrying data provided by the memory device at a period being an integer multiple of the clock signal where the sampling point is different for each sub-part.