Read-Decoupled SRAM Cell for Computing-in-Memory Signal Margin
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Solution Overview
Problem
Conventional SRAM CIM faces challenges in signal margin vs. cell stability, area overhead, process variation, and limited input bandwidth for high-weighted bit operations, particularly in multi-bit convolutional neural network applications.
Innovation Solution
A memory cell design with read-decoupled transistors of varying widths connected to bit lines and word lines, enabling increased signal margin and input bandwidth while reducing area overhead, utilizing a dual-channel scheme to enhance bandwidth and reduce energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 6T SRAM cells are used for CIM operations, then the cell structure is simple and area-efficient, but the signal margin is insufficient and sensing capability is weak
Solution Approach 1:
The SRAM cell is segmented into two distinct transistor types: read-decoupled transistors (first and second) dedicated to read operations with optimized widths for signal margin, and write transistors (third and fourth) dedicated to write operations. This segmentation allows each transistor to be optimized for its specific function, resolving the contradiction between signal margin and area efficiency.
Solution Approach 2:
Different transistors within the same cell are assigned different widths based on their functional requirements. The read-decoupled transistors have widths optimized for read signal margin, while write transistors have widths optimized for write capability. This local quality differentiation enables the cell to achieve both good signal margin and area efficiency.
2Reliability
If read-decoupled transistors with equal widths are used, then the circuit is symmetric and easy to manufacture, but the sensing margin is limited
Solution Approach 1:
The patent changes the width parameter of the second read-decoupled transistor to be twice that of the first read-decoupled transistor. This parameter change optimizes the sensing margin by creating an asymmetric current drive capability during read operations, while the relationship remains a simple integer multiple that is easy to implement in manufacturing.
3Productivity
If conventional SRAM CIM is used, then the implementation is straightforward, but the input bandwidth is limited for multi-bit operations
Solution Approach 1:
The memory cell is designed with multi-functionality to support both traditional read/write operations and CIM operations. The read-decoupled transistors enable the cell to function as both a storage element and a computing element, allowing multi-bit input bandwidth expansion without requiring separate dedicated CIM circuitry, thus improving productivity while controlling complexity.
4Reliability
If larger transistors are used to improve signal margin, then the sensing capability increases, but the area overhead increases
Solution Approach 1:
The cell is segmented into read-decoupled transistors and write transistors with different width optimizations. The read-decoupled transistors have widths specifically optimized for signal margin during read operations, while write transistors have different widths optimized for write operations. This segmentation allows area-efficient design while maintaining good signal margin where needed.
Data Source
AI summary
A memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell includes a plurality of read-decoupled cells. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells.