Read Disturb Tracking Across Shared NAND Erase Blocks
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Solution Overview
Problem
Existing memory systems face challenges in managing read disturb among multiple erase blocks coupled to the same string, leading to increased bit error rates and data loss due to threshold voltage shifts in memory cells.
Innovation Solution
Implementing a system to track and manage read disturb by monitoring the cumulative amount of read operations and program verify operations across erase blocks, using a controller to perform actions such as refreshing or scanning data when a threshold is reached, and applying scaling factors to accurately measure disturb stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple erase blocks are coupled to the same string to increase storage capacity, then the storage density is improved, but read disturb effects accumulate across blocks leading to increased bit error rates
Solution Approach 1:
The patent segments the monitoring and management of read disturb by implementing separate read disturb counters for each erase block coupled to the same string. This allows individual tracking of read operations and program verify operations on each block, enabling precise identification of which blocks are experiencing excessive read disturb stress. The segmentation approach maintains high storage capacity while improving reliability through block-level granularity in disturbance tracking.
Solution Approach 2:
The patent implements a feedback mechanism where the controller continuously monitors read disturb counters for each erase block and compares them against threshold values. When a counter exceeds the threshold, the system triggers corrective actions such as refreshing or scanning affected blocks. This closed-loop feedback system dynamically adjusts memory management based on real-time read disturb conditions, preventing bit error accumulation while maintaining high storage utilization.
2Speed
If read operations are performed frequently to access data, then data accessibility is improved, but read disturb stress accumulates causing threshold voltage shifts in memory cells
Solution Approach 1:
The patent implements preliminary action by proactively monitoring read disturb counters before actual data corruption occurs. The system tracks the cumulative number of read operations and program verify operations on each erase block and compares this count against predetermined thresholds. When the threshold is approached, the system preemptively triggers refresh or scan operations to correct potential threshold voltage shifts before they manifest as bit errors, thus maintaining both fast data access and voltage stability.
Solution Approach 2:
The patent allows rapid data access by permitting read operations to proceed without interruption under normal conditions. The read disturb monitoring operates in the background, and only when thresholds are exceeded does the system intervene with refresh or scan operations. This approach minimizes the impact on data accessibility while still protecting against threshold voltage instability through selective intervention.
3Reliability
If program verify operations are performed to ensure data accuracy, then data integrity is improved, but read disturb effects are amplified due to additional read operations during verification
Solution Approach 1:
The patent incorporates program verify operations into the read disturb monitoring feedback loop. Each program verify operation is counted toward the read disturb counter for the affected erase block, since verify operations involve reading memory cells to check programming accuracy. The system uses this feedback information to determine when refresh or scan operations are needed, balancing the need for data integrity verification against the risk of accumulating read disturb stress from repeated verify reads.
Data Source
AI summary
An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. A controller is configured to monitor a cumulative amount of read disturb stress experienced by a first erase block by: maintaining a read disturb count corresponding to the first erase block; incrementing the read disturb count by a first amount responsive to read commands issued to addresses corresponding to the first erase block; incrementing the read disturb count by a read disturb scaling factor responsive to read commands issued to addresses corresponding to the second erase block; and incrementing the read disturb count by a program scaling factor responsive to program commands issued to addresses corresponding to the second erase block. The controller can perform an action on the first erase block responsive to the read disturb count exceeding a threshold value.