Read Enable Signal Generation Using Data Strobe Signals
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Solution Overview
Problem
As memory systems increase in speed and capacity, they become power-intensive, and conventional methods using DLLs or PLLs to maintain signal integrity are inefficient, leading to high power consumption, especially in multi-rank DRAM systems.
Innovation Solution
A method and device for generating a read enable signal using data strobe signals, which detects whether the data strobe signals are high or low to generate a trigger signal, allowing for proper data transmission without the need for DLLs, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DLLs or PLLs are used to maintain signal timing relationship, then signal transmission reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the DLL/PLL components from the memory system entirely. Instead of using complex phase-locked loops to maintain timing relationships, the invention uses a simplified strobe signal detection mechanism that achieves the same timing synchronization function without the power-consuming DLL/PLL circuitry, thereby resolving the contradiction between reliability and power consumption
Solution Approach 2:
The strobe signal itself serves dual purposes: it both carries the data timing information and acts as the reference for generating the read enable signal. This self-service approach eliminates the need for separate DLL/PLL circuits, maintaining signal timing reliability while dramatically reducing power consumption
2Productivity
If memory system speed and capacity are increased, then productivity is improved, but power consumption and signal integrity issues worsen
Solution Approach 1:
The patent changes the fundamental operating parameter from continuous DLL/PLL phase tracking to discrete strobe signal edge detection. This parameter change allows the system to maintain high-speed operation and timing accuracy without the continuous power consumption associated with traditional phase-locked loop circuits, thus improving productivity while reducing power usage
3Reliability
If DLLs are enabled for every read/write operation to maintain timing, then signal integrity is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent removes the DLL component entirely from the device architecture. The timing synchronization function previously performed by the complex DLL circuit is replaced by a simple strobe signal detection and read enable generation mechanism, thereby maintaining signal integrity while dramatically reducing device complexity
Solution Approach 2:
Instead of using a complex clock recovery mechanism (DLL) to generate timing signals, the patent inverts the approach by using the data strobe signal itself as the timing reference. This inversion simplifies the device architecture while maintaining the necessary timing relationships for signal integrity
Data Source
AI summary
A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generating the read enable signal if the pair of data strobe signals are detected being both high or low. Because the read enable signal is generated using the pair of strobe signals, DLL can be turned off, thus the power consumption of the memory system can be reduced. In addition, the read enable signal is self-aligned with a certain point of the pair of strobe signals, this may enhance precision of the transmission of the pair of strobe signals and the data signal.