Read Gate Training and Tracking for PHY Strobe Alignment
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Solution Overview
Problem
Conventional memory operations in computing systems introduce latency and phase mismatches between the returned data strobe and the PHY clock, leading to inefficiencies in data access and device performance.
Innovation Solution
Implementing read gate training and tracking logic in the PHY, which includes training logic to determine and adjust the phase of the returned data strobe using phase detectors and adjustable delay lines, and tracking logic to compensate for signal drift due to voltage and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory operations are used, then data storage and access functions are provided, but latency is introduced and phase mismatches occur between returned data strobe and PHY clock
Solution Approach 1:
The patent applies preliminary action by performing read gate training before normal memory operations to pre-align the phase relationship between the returned data strobe and PHY clock. The training logic determines optimal delay values in advance, storing them in lookup tables for subsequent use, thereby eliminating the need for real-time phase adjustment during data access operations and reducing operational latency.
Solution Approach 2:
The patent implements feedback through tracking logic that continuously monitors the phase relationship between the returned data strobe and PHY clock during operations. When phase drift is detected due to voltage or temperature variations, the system retrieves pre-determined delay values from lookup tables and adjusts the delay lines accordingly, creating a closed-loop feedback mechanism that maintains synchronization without introducing additional latency.
2Measurement precision
If read gate training and tracking logic is implemented, then phase alignment and sampling accuracy are improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the phase alignment function into separate training logic and tracking logic modules. The training logic handles initial phase calibration, while the tracking logic manages ongoing phase maintenance. This segmentation allows each module to be optimized independently and simplifies the overall control flow, reducing the effective complexity despite the added functionality.
Solution Approach 2:
The patent implements self-service through automatic phase adjustment mechanisms where the tracking logic autonomously monitors phase relationships and triggers delay line adjustments without external intervention. The system uses embedded lookup tables that automatically provide the correct delay values based on detected conditions, eliminating the need for complex external control circuits or manual calibration procedures.
3Stability of the object's composition
If delay adjustment mechanisms are used, then phase matching between strobe and clock is achieved, but signal drift compensation requires additional tracking logic
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal delay compensation values in lookup tables during the training phase. These pre-determined values account for various voltage and temperature conditions, allowing the tracking logic to simply retrieve and apply the appropriate compensation value when drift is detected, rather than performing complex real-time calculations.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the delay line parameters based on detected phase drift and lookup table recommendations. The system changes the delay parameter values to compensate for environmental variations, maintaining stable phase relationships without requiring complex adaptive algorithms during operation.
Data Source
AI summary
In accordance with described techniques for read gate training and tracking, a computing device includes a memory system (e.g., dynamic random access memory (DRAM)) that receives a memory read operation which includes a memory clock that correlates to a physical layer (PHY) clock. The computing device includes a PHY that receives a return data signal from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock. The computing device includes training logic that utilizes edge detection to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock. The computing device also includes tracking logic that utilizes the edge detection to detect a signal drift of the delay signal with respect to the returned data strobe and compensate for the drift.