Read Hints for Preloading PIM Results into Processor Caches
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Solution Overview
Problem
Offloading computations to memory using Processing In Memory (PIM) technology leads to increased cache flushes and cache misses, which offset performance benefits and incur additional latency due to kernel launches and prefetches in GPU and CPU contexts.
Innovation Solution
Implementing read hints in memory-side processing instructions to preload results into processor-side caches, allowing cache controllers to proactively store memory-side processing results, thereby reducing cache misses and avoiding serialization on the critical processor path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computations are offloaded to memory using PIM technology, then data bus traffic and computational burdens on processors are reduced, but cache flushes and cache misses increase
Solution Approach 1:
The patent applies preliminary action by preloading data into processor-side caches before PIM computations are executed. The system identifies data that will be needed for subsequent processor computations and loads it into caches in advance, so that when the PIM computation completes and results are written back to memory, the data is already available in caches rather than requiring cache flushes. This eliminates the latency penalty associated with cache synchronization.
2Productivity
If results of PIM-based computations are stored in memory, then computational capacity is utilized, but processor-side caches experience cache misses
Solution Approach 1:
The system performs preliminary loading of data into processor-side caches before the PIM computation occurs. By identifying which data will be needed for subsequent processor operations and preloading it into caches, the system ensures that when results are written back from memory, the relevant data is already cached, avoiding cache misses and their associated performance penalties.
3Reliability
If prefetch functions or kernel launches are used to preload computation results, then cache availability is improved, but latency and serialization increase
Solution Approach 1:
The patent implements self-service by enabling the cache controller to automatically detect when data has been modified by PIM operations and autonomously invalidate or update the relevant cache lines. This eliminates the need for software-initiated prefetch operations or kernel launches, as the cache system automatically maintains consistency. The burden of cache management is shifted from the processor software to the hardware cache controller, reducing latency and avoiding serialization on the critical processor path.
Solution Approach 2:
The system uses feedback mechanisms where the cache controller monitors memory access patterns and PIM computation completion status. When a PIM computation completes and writes results back to memory, the cache controller receives feedback about which memory addresses were modified and automatically updates its internal state to reflect these changes, enabling it to proactively manage cache validity without processor intervention.
Data Source
AI summary
A technical solution to the technical problem of how to reduce the undesirable side effects of offloading computations to memory uses read hints to preload results of memory-side processing into a processor-side cache. A cache controller, in response to identifying a read hint in a memory-side processing instruction, causes results of the memory-side processing to be preloaded into a processor-side cache. Implementations include, without limitation, enabling or disabling the preloading based upon cache thrashing levels, preloading results, or portions of results, of memory-side processing to particular destination caches, preloading results based upon priority and/or degree of confidence, and/or during periods of low data bus and/or command bus utilization, last stores considerations, and enforcing an ordering constraint to ensure that preloading occurs after memory-side processing results are complete.