Read Interface Re-Sync Clock Calibration Using Toggle Read Paths
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Solution Overview
Problem
Existing methods for calibrating clock signals across clock domain boundaries require writing and reading data, which can delay the process and overwrite existing memory contents, and do not efficiently adjust the phase of the destination-synchronous clock signal relative to the source-synchronous clock signal to minimize read errors.
Innovation Solution
Configurable read interface circuitry with multiplexors and capture registers allows for the generation of toggle signals to determine the preferred phase of the destination-synchronous clock signal, enabling phase calibration without overwriting memory and reducing calibration delays by using existing read paths for both data and calibration signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data is written to the source device and read back for calibration, then the re-sync clock can be calibrated, but the calibration process is delayed and existing memory contents are overwritten
Solution Approach 1:
The patent creates a copy of the data path by using the inverted output of the capture register fed back through a multiplexor to the toggle register input. This allows calibration signals to be generated without actually writing to or reading from the source device memory, eliminating the time-consuming data transfer while maintaining calibration accuracy
Solution Approach 2:
The patent introduces an intermediary toggle signal generated by the toggle register that mediates between the capture register and the calibration process. This toggle signal serves as a proxy for actual data, allowing phase calibration to proceed without requiring real data writes and reads, thus reducing calibration time while maintaining precision
2Measurement precision
If data is written to the source device for calibration, then the re-sync clock can be calibrated, but existing memory contents are overwritten
Solution Approach 1:
The patent uses a copied signal path where the inverted output of the capture register is fed back through a multiplexor to generate a toggle signal. This copying approach eliminates the need to actually write calibration data to memory, preserving existing memory contents while still enabling accurate clock phase calibration through the toggle signal mechanism
3Reliability
If write calibration is completed first to ensure accurate data writing, then data integrity is maintained, but the overall calibration process is delayed
Solution Approach 1:
The patent eliminates the sequential write-then-read calibration sequence by using a copied signal path. The inverted capture register output fed back through the multiplexor creates a toggle signal that directly enables phase calibration without requiring prior write calibration, thus maintaining data integrity through the toggle mechanism while eliminating the time delay of sequential calibration steps
Solution Approach 2:
The patent performs preliminary configuration of the multiplexor to select the inverted capture register output path before calibration begins. This preliminary setup enables the toggle signal generation to proceed immediately without waiting for write calibration completion, thus maintaining reliability through proper signal routing while reducing the overall calibration time by eliminating sequential dependencies
Data Source
AI summary
Read interface circuitry is disclosed that facilitates using a source-synchronous clock signal to calibrate the read interface. In one embodiment, configurable read interface circuitry allows a particular read path to be configured for use in calibrating a read interface of the destination device. In particular, a plurality of read paths are provided, each read path having a configurable multiplexor (“mux”) coupled to a capture register of the read path such that the mux can be configured to select either an input coupled to an inverted output of the capture register or an input coupled to a prior register in the read data path. When the inverted output of the capture register is selected, a source-synchronous clock signal (e.g., DQS or delayed DQS signal) provided at the capture register's clock input results in a toggle signal at the capture register's output. In one embodiment, that toggle signal is provided to a re-sync register clocked by a re-sync clock signal. This toggle signal, together with another toggle signal generated at a toggle register coupled to the re-sync clock signal, are compared for various possible phases of the re-sync clock signal to determine a preferred phase of the re-sync clock signal. For other read paths, a mux coupled to a similar capture register is configured to select an input coupled to a prior register in the read path so that the read path can act as a path for incoming data signals (e.g., DQ signals).