Read Latency Control Circuit With Synchronized Internal Clocking
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Solution Overview
Problem
High-speed DRAMs face challenges in maintaining precise read latency due to indeterminable read clock delay relative to read data valid time, leading to difficulties in ensuring correct data output and specified read latency, which is exacerbated by the need for large and cumbersome DLL circuits that consume valuable chip space.
Innovation Solution
A read latency control circuit utilizing a synchronization circuit to generate internal clock signals that synchronize read data with an external clock signal, eliminating the need for additional circuitry like slave delay circuits by using upstream and downstream clock signals to track clock pulses and achieve the specified read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a DLL circuit is used to generate internal clock signals for synchronizing read data with external clock, then read latency control is improved, but chip area consumption increases due to large and cumbersome DLL circuits
Solution Approach 1:
The patent extracts the essential timing control function from the traditional DLL circuit by using a minimal delay element (single inverter or buffer) to generate the read clock signal. This extraction removes the cumbersome DLL circuitry while retaining the core functionality of synchronizing read data with the external clock signal, thereby reducing chip area while maintaining read latency precision.
Solution Approach 2:
The patent creates a simplified copy of the DLL timing control mechanism by using a delay element that replicates the essential phase adjustment function. Instead of implementing a full DLL circuit, a single delay element copies the necessary timing relationship between external clock and read data, achieving the same synchronization effect with minimal area overhead.
2Reliability
If traditional DLL circuits are used to align read data with external clock, then timing synchronization is improved, but device complexity increases due to additional circuitry requirements
Solution Approach 1:
The patent extracts only the essential timing alignment function from the traditional DLL circuit, removing unnecessary complexity. By using a single delay element to generate the read clock signal with proper phase relationship, the invention maintains reliable timing synchronization while dramatically reducing circuit complexity compared to full DLL implementations.
Solution Approach 2:
The delay element automatically adjusts the read clock signal phase based on the external clock signal characteristics, providing self-service timing synchronization. The circuit inherently compensates for timing variations without requiring complex control logic or additional synchronization circuitry, thereby maintaining reliability while simplifying the overall device architecture.
3Speed
If read clock delay is made indeterminable for high speed operations, then operating speed is improved, but read latency control becomes difficult
Solution Approach 1:
The patent implements a dynamic read clock signal generation approach where the delay element continuously adapts to high-speed operating conditions. The read clock signal is generated with a delay that dynamically responds to external clock variations, allowing the circuit to maintain precise read latency control even as operating speed increases and timing relationships become more critical.
Solution Approach 2:
The patent changes the timing parameters of the read clock signal by introducing a controlled delay through the delay element. This parameter adjustment allows the read clock to be properly aligned with read data valid time despite high-speed operations, maintaining determinable and precise read latency while supporting increased operating speeds through optimized delay characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively synchronizes read data with the external clock signal, ensuring precise read latency while reducing chip area consumption by eliminating unnecessary circuitry, thus improving high-speed operations and maintaining data integrity.
Implementation Method 1
an internal clock signal is developed in response to the external clock signal, and is conventionally applied to latches contained in the memory device to clock the external signals into the latches. The internal clock signal and external clock signal must be synchronized to ensure the latches are clocked at the proper times
Implementation Method 2
synchronizing the variable timing of the internal clock signals derived from an external clock signal such that the read data and the read clock signal used to latch the read data arrive at the data latch in synchronism and with a specified read latency
Data Source
AI summary
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.