Read Latency Control Circuit Using Synchronized Clock Tracking
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Solution Overview
Problem
High-speed DRAMs face challenges in maintaining precise read latency due to indeterminable read clock delay, leading to difficulties in ensuring correct data output and specified read latency, which is exacerbated by the need for additional circuitry that consumes valuable chip space.
Innovation Solution
A read latency control circuit utilizing a synchronization circuit to generate internal clock signals that synchronize read data with an external clock signal, eliminating the need for additional circuitry like slave delay circuits by using upstream and downstream clock signals to track clock pulses and achieve the specified read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional circuitry like slave delay circuits is used to maintain precise read latency, then read latency precision is improved, but chip space consumption increases
Solution Approach 1:
The patent uses a copy of the DLL circuit (slave delay circuit) to model and track the delay characteristics of the main DLL. This copy circuit replicates the delay behavior without requiring full delay model implementation, thereby maintaining read latency precision while reducing chip space consumption compared to comprehensive delay modeling approaches.
Solution Approach 2:
The patent introduces an intermediary tracking mechanism that uses the relationship between upstream and downstream clock signals to indirectly determine read latency. Instead of directly measuring or modeling all delay paths, the intermediary counter tracks clock pulse differences, serving as a mediator that simplifies the complexity and reduces the circuit area required for latency control.
2Reliability
If comprehensive delay models are implemented to ensure correct data output, then data output accuracy is improved, but device complexity increases
Solution Approach 1:
Rather than implementing comprehensive delay models for the entire DLL system, the patent creates a simplified copy (slave delay circuit) that captures the essential delay characteristics. This copy is used to generate tracking signals that maintain data output accuracy without requiring the full complexity of complete delay modeling across all circuit paths.
Solution Approach 2:
The patent extracts only the critical delay tracking function from the comprehensive delay model requirement. By separating the essential latency tracking capability from the full delay modeling complexity, the system achieves data output accuracy through a simplified mechanism that focuses only on the necessary delay compensation without unnecessary circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively maintains precise read latency while reducing chip area consumption, ensuring accurate data output even at high speeds without the need for cumbersome delay models.
Implementation Method 1
a delay locked loop, which generates internal clock signals for the memory device, including the read clock signal
Implementation Method 2
A read latency control circuit utilizing a synchronization circuit to generate internal clock signals that synchronize read data with an external clock signal
Data Source
AI summary
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.