Read Latency Control Circuit Using DLL Clock Synchronization
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Solution Overview
Problem
High-speed DRAMs face challenges in maintaining precise read latency due to indeterminable read clock delay, leading to difficulties in ensuring correct data output and specified read latency, which is exacerbated by the need for additional circuitry that consumes valuable chip space.
Innovation Solution
A read latency control circuit utilizing a synchronization circuit with upstream and downstream clock signals (CLKUP and CLKDN) generated by a delay locked loop (DLL) to synchronize internal clock pulses with external clock signals, eliminating the need for additional slave delay circuits and reducing chip space consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional slave delay circuits are added to synchronize read clock and data, then read latency precision is improved, but chip space consumption increases
Solution Approach 1:
The patent combines the delay generation function and synchronization function into a single integrated delay locked loop circuit. The DLL generates both the read clock signal and the delayed data signal using shared delay elements and a single phase detector, eliminating the need for separate slave delay circuits while maintaining synchronization precision.
Solution Approach 2:
The delay locked loop circuit performs multiple functions simultaneously: it generates the read clock signal, delays the read data, and provides synchronization control. This multi-functional approach replaces what would traditionally require multiple dedicated circuits, reducing overall chip space while maintaining read latency precision.
2Speed
If read clock delay is increased to accommodate high speed operations, then data transfer speed is improved, but read latency control precision deteriorates
Solution Approach 1:
The phase detector in the DLL continuously monitors the phase relationship between the read clock and delayed data signals, providing feedback control. This feedback mechanism allows the system to maintain precise read latency control even as delay values are adjusted for high-speed operations, automatically correcting any drift or errors.
Solution Approach 2:
The delay elements in the DLL are designed to be dynamically adjustable, allowing the read clock and data delays to be optimized for different operating speeds. The continuous phase adjustment capability enables the system to adapt to varying speed requirements while maintaining precision through the feedback-controlled phase detector.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively synchronizes read data with the external clock signal, ensuring precise read latency is met without the need for extra circuitry, thus maintaining data integrity and optimizing chip space in high-speed memory devices.
Implementation Method 1
A read latency control circuit utilizing a synchronization circuit with upstream and downstream clock signals (CLKUP and CLKDN) generated by a delay locked loop (DLL) to synchronize internal clock pulses with external clock signals
Data Source
AI summary
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.