Read Latency Control Circuit Using DLL Clock Synchronization
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Solution Overview
Problem
High-speed DRAMs face challenges in maintaining precise read latency due to indeterminable read clock delay, leading to difficulties in ensuring correct data output and specified read latency, which is exacerbated by the need for additional circuitry that consumes valuable chip space.
Innovation Solution
A read latency control circuit utilizing a synchronization circuit that generates upstream and downstream clock signals to synchronize internal read clock pulses with external clock signals, eliminating the need for additional circuitry like slave delay circuits and reducing chip space consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional circuitry like slave delay circuits is used to synchronize read clock and read data, then read latency control precision is improved, but chip space consumption increases
Solution Approach 1:
The patent merges the DLL circuit and read latency control circuit into a unified structure where the DLL serves dual purposes: both clock synchronization and read latency control. The read latency control circuit shares the DLL-generated clock signals and uses the same delay mechanisms, eliminating the need for separate slave delay circuits while maintaining precise read latency control.
Solution Approach 2:
The DLL circuit is designed to perform multiple functions simultaneously: it generates synchronized clock signals for the memory device and provides the delay control for read latency. The same delay elements and control logic are used for both clock synchronization and read data timing, making the circuit multi-functional and reducing overall chip space requirements.
2Productivity
If high-speed operations are implemented, then productivity is improved, but read clock delay becomes indeterminable making latency control difficult
Solution Approach 1:
The patent implements a feedback mechanism where the read latency control circuit continuously monitors the timing relationship between read clock signals and read data signals. Based on this feedback, the control circuit adjusts the delay of the read clock signal dynamically to maintain precise read latency control even during high-speed operations where fixed delay models become inaccurate.
Solution Approach 2:
The read latency control circuit uses dynamic delay adjustment rather than fixed delay values. The delay amount is continuously adapted based on actual timing measurements and feedback from the operating conditions, allowing the system to maintain precise latency control across varying speeds and conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively synchronizes read data with the specified read latency, ensuring accurate data output while minimizing chip area usage, thus addressing the challenges of high-speed operations in DRAMs.
Implementation Method 1
The memory device has its own internal clock system, which receives the external clock signal and develops from the external clock signal several different internal clock signals using a delay locked loop ('DLL').
Data Source
AI summary
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.