Read-Modify-Write Memory Circuit Error Correction
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Solution Overview
Problem
Semiconductor devices face increased error probability due to faster data transmission speeds, necessitating advanced design schemes to guarantee data transmission reliability, particularly during read-modify-write operations where internal data corrections are required.
Innovation Solution
A semiconductor memory device incorporating a read/write control circuit and an error correction circuit that generates internal write signals and corrects errors by performing logical operations on internal read and write data, with voltage control circuits adjusting supply voltages based on internal delay times and clock signal frequencies to optimize data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal is increased to improve operation speed, then data transmission speed is improved, but error probability increases
Solution Approach 1:
The patent applies preliminary action by performing a read operation before the write operation in the read-modify-write sequence. The internal read signal is generated to read existing data from the memory cell before the internal write signal is generated to write new data. This preliminary reading allows the system to prepare for potential error correction by having the original data available for comparison and correction operations.
2Reliability
If error correction codes are generated and transmitted with data to guarantee reliability, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error correction functionality with the existing read-modify-write operation sequence. The error correction circuit is integrated into the memory device and operates using the same internal read and write signals. The correction operation combines the read data and write data through logical operations to generate corrected write data, merging multiple functions (reading, writing, error correction) into a unified operation sequence that reduces overall system complexity.
Solution Approach 2:
The read-modify-write operation serves multiple functions simultaneously: it updates memory data, performs error detection through comparison of read and write data, and enables error correction through logical operations. This multi-functionality eliminates the need for separate error correction operations, reducing device complexity while maintaining reliability.
3Adaptability or versatility
If internal read and write operations are performed at different times, then operation flexibility is improved, but timing synchronization becomes difficult
Solution Approach 1:
The patent applies dynamics by making the timing of internal read and write signals adaptive to the clock signal frequency. The read/write control circuit dynamically adjusts the generation timing of internal read and write signals based on the actual clock frequency. This dynamic timing adjustment maintains proper synchronization between read and write operations while allowing flexibility in when these operations occur within the clock cycle, resolving the contradiction between timing synchronization and operation flexibility.
Data Source
AI summary
A semiconductor memory device includes a read/write control circuit and an error correction circuit. The read/write control circuit generates an internal write signal after generating an internal read signal from one of a plurality of shifted signals which are generated by shifting a read-modify-write command according to a frequency of a clock signal. The error correction circuit corrects an error included in internal data by performing a logical operation of read data generated by the internal read signal and the internal data to generate write data. The internal read signal is enabled by a write set signal during the read-modify-write operation.