Read Voltage Offset Tuning for Partial Memory Block Errors
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Solution Overview
Problem
Non-volatile memory devices experience increased read errors due to threshold voltage shifting in partial blocks, which are physically open but logically closed, leading to higher error rates and the need for error recovery mechanisms.
Innovation Solution
Applying read voltage offsets to compensate for threshold voltage shifts in memory cells, particularly in partial blocks, by adjusting the magnitude of read voltage offsets based on word line utilization and cell levels to reduce read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read operations are performed on partial blocks without voltage offset compensation, then device complexity is reduced, but read error rate increases
Solution Approach 1:
The patent applies parameter changes by adjusting the read voltage offset based on the block type (partial block vs. full block) and word line position. The controller dynamically modifies the read voltage parameter to compensate for threshold voltage shifts in partial blocks, thereby reducing read errors without requiring fundamental changes to the memory device architecture.
Solution Approach 2:
The patent implements dynamics by making the read voltage offset adaptive rather than static. The controller determines the block type and selects different voltage offset values dynamically during read operations. This allows the system to optimize read accuracy for partial blocks while maintaining normal operation for full blocks, resolving the contradiction between reliability and complexity.
2Reliability
If threshold voltage shifts are compensated with fixed voltage offsets, then read errors are reduced, but adaptability to different block types deteriorates
Solution Approach 1:
The patent applies local quality by implementing different read voltage offset values for different block types (partial blocks vs. full blocks) and different word line positions within those blocks. Rather than using a uniform offset across all scenarios, the system tailors the voltage compensation locally to match the specific threshold voltage shift characteristics of each block type, thereby maintaining high adaptability while reducing read errors.
Solution Approach 2:
The patent makes the voltage offset adaptive by dynamically selecting offset values based on the determined block type. The controller adjusts the read voltage parameter in real-time according to whether the block is a partial or full block, ensuring optimal read accuracy for each scenario without sacrificing adaptability to different block configurations.
3Reliability
If error recovery mechanisms are implemented for partial blocks, then data integrity is maintained, but device complexity and operation time increase
Solution Approach 1:
The patent applies preliminary action by proactively compensating for threshold voltage shifts through voltage offset adjustment before read errors can occur. By pre-characterizing partial blocks and applying appropriate voltage offsets during read operations, the system prevents errors rather than requiring post-error recovery mechanisms, thereby maintaining data integrity while reducing complexity and operation time.
Solution Approach 2:
The patent converts the harmful effect of threshold voltage shifts in partial blocks into a beneficial outcome by characterizing and compensating for these shifts through voltage offset adjustment. What would normally be a source of errors requiring complex recovery mechanisms becomes a manageable parameter that can be corrected through simple voltage adjustment, thereby maintaining data integrity with minimal added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces the likelihood and rate of read errors, minimizes the need for error recovery, and maintains data integrity by accounting for threshold voltage variations in partial blocks.
Implementation Method 1
applying a high positive voltage, which may be referred to as a 'program voltage,' a 'programming power voltage,' or 'VPP,' to a control gate to generate Fowler-Nordheim tunneling (referred to as 'F-N tunneling') between a floating gate and the semiconductor substrate. When F-N tunneling is occurring, electrons of the bulk area are accumulated on the floating gate by an electric field of VPP applied to the control gate to increase a threshold voltage of the memory cell.
Implementation Method 2
An erasing operation of the memory cell is concurrently performed in units of sectors sharing the bulk area (referred to as 'blocks' or 'memory blocks'), by applying a high negative voltage, which may be referred to as an 'erase voltage' or 'Vera,' to the control gate and a configured voltage to the bulk area to generate the F-N tunneling.
Data Source
AI summary
A memory device may include a memory and a controller. The controller may be configured to receive a read command associated with a block of the memory. The controller may be configured to determine a block type associated with the block. The controller may be configured to identify, based on the block type, one or more read voltage offsets for a read operation associated with the block. The controller may be configured to perform the read operation based on the one or more read voltage offsets.